Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T17,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T218	Yes	T55,T56,T218	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T55,T56,T218	Yes	T55,T56,T218	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T79,*T80	Yes	T70,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T70,T9,T81	Yes	T70,T9,T81	INPUT
tl_i.a_valid	Yes	Yes	T55,T56,T218	Yes	T55,T56,T218	INPUT
tl_o.a_ready	Yes	Yes	T55,T56,T218	Yes	T55,T56,T218	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T55,T56,T218	Yes	T55,T56,T218	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T55,T56,T218	Yes	T55,T56,T218	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T55,T56,T218	Yes	T55,T56,T218	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T81,*T76,*T77	Yes	T81,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T55,*T56,*T218	Yes	T55,T56,T218	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T55,T56,T218	Yes	T55,T56,T218	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T178,T317	Yes	T18,T178,T317	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T163,T83,T84	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T163,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T178,T317	Yes	T18,T178,T317	OUTPUT
cio_rx_i	Yes	Yes	T4,T17,T44	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T55,T56,T218	Yes	T55,T56,T218	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T218,T293,T150	Yes	T218,T293,T150	OUTPUT
intr_tx_empty_o	Yes	Yes	T218,T293,T150	Yes	T218,T293,T150	OUTPUT
intr_rx_watermark_o	Yes	Yes	T218,T293,T150	Yes	T218,T293,T150	OUTPUT
intr_tx_done_o	Yes	Yes	T218,T293,T150	Yes	T218,T293,T150	OUTPUT
intr_rx_overflow_o	Yes	Yes	T218,T293,T150	Yes	T218,T293,T150	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T17,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T293	Yes	T55,T56,T293	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T55,T56,T293	Yes	T55,T56,T293	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T79,*T80	Yes	T70,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T70,T9,T81	Yes	T70,T9,T81	INPUT
tl_i.a_valid	Yes	Yes	T55,T56,T293	Yes	T55,T56,T293	INPUT
tl_o.a_ready	Yes	Yes	T55,T56,T293	Yes	T55,T56,T293	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T55,T56,T293	Yes	T55,T56,T293	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T55,T56,T293	Yes	T55,T56,T293	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T55,T56,T293	Yes	T55,T56,T293	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T81,*T77,*T78	Yes	T81,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T55,*T56,*T293	Yes	T55,T56,T293	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T55,T56,T293	Yes	T55,T56,T293	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T317,T163,T60	Yes	T317,T163,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T163,T83,T84	Yes	T83,T84,T164	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T164	Yes	T163,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T317,T163,T60	Yes	T317,T163,T60	OUTPUT
cio_rx_i	Yes	Yes	T4,T17,T44	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T293,T308,T222	Yes	T293,T308,T222	OUTPUT
intr_tx_empty_o	Yes	Yes	T293,T308,T222	Yes	T293,T308,T222	OUTPUT
intr_rx_watermark_o	Yes	Yes	T293,T308,T222	Yes	T293,T308,T222	OUTPUT
intr_tx_done_o	Yes	Yes	T293,T308,T222	Yes	T293,T308,T222	OUTPUT
intr_rx_overflow_o	Yes	Yes	T293,T308,T222	Yes	T293,T308,T222	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T17,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T79,*T80	Yes	T70,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T70,T9,T81	Yes	T70,T9,T81	INPUT
tl_i.a_valid	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	INPUT
tl_o.a_ready	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	OUTPUT
tl_o.d_error	Yes	Yes	T76,T78,T158	Yes	T76,T78,T158	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T81,*T76,*T78	Yes	T81,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T218,*T293,*T308	Yes	T218,T293,T308	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T178,T60,T83	Yes	T178,T60,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T178,T60,T83	Yes	T178,T60,T83	OUTPUT
cio_rx_i	Yes	Yes	T218,T45,T323	Yes	T218,T23,T45	INPUT
cio_tx_o	Yes	Yes	T218,T323,T324	Yes	T218,T323,T324	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	OUTPUT
intr_tx_empty_o	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	OUTPUT
intr_rx_watermark_o	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	OUTPUT
intr_tx_done_o	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	OUTPUT
intr_rx_overflow_o	Yes	Yes	T218,T293,T308	Yes	T218,T293,T308	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T17,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T79,*T80	Yes	T70,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T70,T9,T81	Yes	T70,T9,T81	INPUT
tl_i.a_valid	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	INPUT
tl_o.a_ready	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T158	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T158	Yes	T77,T78,T158	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T81,*T77,*T78	Yes	T81,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T158	Yes	T77,T78,T158	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T293,*T150,*T308	Yes	T293,T150,T308	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T83,T84	Yes	T60,T83,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T83,T84	Yes	T60,T83,T84	OUTPUT
cio_rx_i	Yes	Yes	T150,T151,T325	Yes	T150,T151,T325	INPUT
cio_tx_o	Yes	Yes	T150,T151,T325	Yes	T150,T151,T325	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	OUTPUT
intr_tx_empty_o	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	OUTPUT
intr_rx_watermark_o	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	OUTPUT
intr_tx_done_o	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	OUTPUT
intr_rx_overflow_o	Yes	Yes	T293,T150,T308	Yes	T293,T150,T308	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T17,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T79,*T80	Yes	T70,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T70,T9,T81	Yes	T70,T9,T81	INPUT
tl_i.a_valid	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	INPUT
tl_o.a_ready	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T81,*T78,*T82	Yes	T81,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T82,T158	Yes	T78,T82,T158	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T293,*T30,*T308	Yes	T293,T30,T308	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T339,T666	Yes	T18,T339,T666	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T339,T666	Yes	T18,T339,T666	OUTPUT
cio_rx_i	Yes	Yes	T30,T31,T310	Yes	T30,T31,T310	INPUT
cio_tx_o	Yes	Yes	T30,T31,T310	Yes	T30,T31,T310	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	OUTPUT
intr_tx_empty_o	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	OUTPUT
intr_rx_watermark_o	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	OUTPUT
intr_tx_done_o	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	OUTPUT
intr_rx_overflow_o	Yes	Yes	T293,T30,T308	Yes	T293,T30,T308	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T308,T309	Yes	T293,T308,T309	OUTPUT

*Tests covering at least one bit in the range