Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T23,T45,T26 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T23,T45,T26 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T23,T45,T26 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
13481 |
13023 |
0 |
0 |
selKnown1 |
119744 |
118429 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
13481 |
13023 |
0 |
0 |
T21 |
4 |
3 |
0 |
0 |
T22 |
6 |
5 |
0 |
0 |
T26 |
19 |
18 |
0 |
0 |
T27 |
203 |
202 |
0 |
0 |
T29 |
33 |
32 |
0 |
0 |
T42 |
18 |
16 |
0 |
0 |
T43 |
10 |
8 |
0 |
0 |
T48 |
10 |
24 |
0 |
0 |
T58 |
31 |
30 |
0 |
0 |
T59 |
1 |
0 |
0 |
0 |
T68 |
1 |
0 |
0 |
0 |
T69 |
1 |
0 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T72 |
0 |
67 |
0 |
0 |
T73 |
0 |
48 |
0 |
0 |
T119 |
0 |
1 |
0 |
0 |
T120 |
1 |
0 |
0 |
0 |
T170 |
1 |
0 |
0 |
0 |
T171 |
0 |
3 |
0 |
0 |
T195 |
9 |
8 |
0 |
0 |
T196 |
5 |
4 |
0 |
0 |
T197 |
3 |
2 |
0 |
0 |
T198 |
3 |
2 |
0 |
0 |
T199 |
6 |
5 |
0 |
0 |
T200 |
3 |
2 |
0 |
0 |
T201 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
119744 |
118429 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T17 |
2 |
1 |
0 |
0 |
T18 |
2 |
1 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T41 |
45 |
43 |
0 |
0 |
T42 |
4 |
8 |
0 |
0 |
T43 |
11 |
29 |
0 |
0 |
T44 |
2 |
1 |
0 |
0 |
T45 |
545 |
544 |
0 |
0 |
T48 |
10 |
26 |
0 |
0 |
T55 |
1 |
0 |
0 |
0 |
T64 |
2 |
1 |
0 |
0 |
T87 |
1 |
0 |
0 |
0 |
T159 |
0 |
1 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
T178 |
0 |
1 |
0 |
0 |
T183 |
0 |
1 |
0 |
0 |
T195 |
22 |
35 |
0 |
0 |
T196 |
6 |
18 |
0 |
0 |
T197 |
5 |
9 |
0 |
0 |
T198 |
7 |
6 |
0 |
0 |
T199 |
11 |
10 |
0 |
0 |
T200 |
8 |
7 |
0 |
0 |
T202 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T23,T7,T29 |
0 | 1 | Covered | T23,T7,T29 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T23,T7,T29 |
1 | 1 | Covered | T23,T7,T29 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
904 |
783 |
0 |
0 |
T21 |
4 |
3 |
0 |
0 |
T22 |
6 |
5 |
0 |
0 |
T29 |
33 |
32 |
0 |
0 |
T58 |
31 |
30 |
0 |
0 |
T59 |
1 |
0 |
0 |
0 |
T68 |
1 |
0 |
0 |
0 |
T69 |
1 |
0 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T72 |
0 |
67 |
0 |
0 |
T73 |
0 |
48 |
0 |
0 |
T119 |
0 |
1 |
0 |
0 |
T120 |
1 |
0 |
0 |
0 |
T170 |
1 |
0 |
0 |
0 |
T171 |
0 |
3 |
0 |
0 |
T201 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1688 |
712 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T17 |
2 |
1 |
0 |
0 |
T18 |
2 |
1 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T44 |
2 |
1 |
0 |
0 |
T55 |
1 |
0 |
0 |
0 |
T64 |
2 |
1 |
0 |
0 |
T87 |
1 |
0 |
0 |
0 |
T159 |
0 |
1 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
T178 |
0 |
1 |
0 |
0 |
T183 |
0 |
1 |
0 |
0 |
T202 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T27,T28,T203 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T23,T45,T26 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T27,T28,T203 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1452 |
1435 |
0 |
0 |
selKnown1 |
1774 |
1754 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1452 |
1435 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T26 |
19 |
18 |
0 |
0 |
T27 |
203 |
202 |
0 |
0 |
T28 |
206 |
205 |
0 |
0 |
T41 |
9 |
8 |
0 |
0 |
T42 |
11 |
10 |
0 |
0 |
T43 |
6 |
5 |
0 |
0 |
T48 |
0 |
15 |
0 |
0 |
T203 |
657 |
656 |
0 |
0 |
T204 |
219 |
218 |
0 |
0 |
T205 |
19 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1774 |
1754 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T41 |
23 |
22 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
19 |
0 |
0 |
T45 |
545 |
544 |
0 |
0 |
T46 |
545 |
544 |
0 |
0 |
T47 |
545 |
544 |
0 |
0 |
T48 |
0 |
17 |
0 |
0 |
T195 |
0 |
14 |
0 |
0 |
T196 |
0 |
13 |
0 |
0 |
T197 |
0 |
5 |
0 |
0 |
T203 |
1 |
0 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
T205 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T23,T24,T25 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T23,T45,T46 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T23,T24,T25 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
54 |
41 |
0 |
0 |
T42 |
7 |
6 |
0 |
0 |
T43 |
4 |
3 |
0 |
0 |
T48 |
10 |
9 |
0 |
0 |
T195 |
9 |
8 |
0 |
0 |
T196 |
5 |
4 |
0 |
0 |
T197 |
3 |
2 |
0 |
0 |
T198 |
3 |
2 |
0 |
0 |
T199 |
6 |
5 |
0 |
0 |
T200 |
3 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112 |
96 |
0 |
0 |
T41 |
22 |
21 |
0 |
0 |
T42 |
4 |
3 |
0 |
0 |
T43 |
11 |
10 |
0 |
0 |
T48 |
10 |
9 |
0 |
0 |
T195 |
22 |
21 |
0 |
0 |
T196 |
6 |
5 |
0 |
0 |
T197 |
5 |
4 |
0 |
0 |
T198 |
7 |
6 |
0 |
0 |
T199 |
11 |
10 |
0 |
0 |
T200 |
8 |
7 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T27,T28,T203 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T45,T46,T47 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T27,T28,T203 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1463 |
1447 |
0 |
0 |
selKnown1 |
122 |
109 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1463 |
1447 |
0 |
0 |
T26 |
19 |
18 |
0 |
0 |
T27 |
209 |
208 |
0 |
0 |
T28 |
197 |
196 |
0 |
0 |
T41 |
10 |
9 |
0 |
0 |
T42 |
13 |
12 |
0 |
0 |
T43 |
4 |
3 |
0 |
0 |
T48 |
17 |
16 |
0 |
0 |
T203 |
667 |
666 |
0 |
0 |
T204 |
218 |
217 |
0 |
0 |
T205 |
19 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122 |
109 |
0 |
0 |
T41 |
19 |
18 |
0 |
0 |
T42 |
11 |
10 |
0 |
0 |
T43 |
12 |
11 |
0 |
0 |
T45 |
2 |
1 |
0 |
0 |
T46 |
2 |
1 |
0 |
0 |
T47 |
2 |
1 |
0 |
0 |
T48 |
12 |
11 |
0 |
0 |
T195 |
12 |
11 |
0 |
0 |
T196 |
15 |
14 |
0 |
0 |
T197 |
9 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T23,T41,T42 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T45,T46,T24 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T23,T41,T42 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50 |
39 |
0 |
0 |
T42 |
4 |
3 |
0 |
0 |
T43 |
4 |
3 |
0 |
0 |
T48 |
10 |
9 |
0 |
0 |
T195 |
7 |
6 |
0 |
0 |
T196 |
3 |
2 |
0 |
0 |
T198 |
5 |
4 |
0 |
0 |
T199 |
11 |
10 |
0 |
0 |
T200 |
3 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
110 |
96 |
0 |
0 |
T41 |
20 |
19 |
0 |
0 |
T42 |
9 |
8 |
0 |
0 |
T43 |
10 |
9 |
0 |
0 |
T48 |
11 |
10 |
0 |
0 |
T195 |
13 |
12 |
0 |
0 |
T196 |
8 |
7 |
0 |
0 |
T197 |
8 |
7 |
0 |
0 |
T198 |
6 |
5 |
0 |
0 |
T199 |
11 |
10 |
0 |
0 |
T200 |
10 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T23,T26,T27 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T41,T42,T43 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T23,T26,T27 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1782 |
1764 |
0 |
0 |
selKnown1 |
143 |
133 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1782 |
1764 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T27 |
348 |
347 |
0 |
0 |
T28 |
319 |
318 |
0 |
0 |
T41 |
6 |
5 |
0 |
0 |
T42 |
11 |
10 |
0 |
0 |
T43 |
4 |
3 |
0 |
0 |
T48 |
14 |
13 |
0 |
0 |
T195 |
0 |
17 |
0 |
0 |
T196 |
0 |
16 |
0 |
0 |
T203 |
641 |
640 |
0 |
0 |
T204 |
347 |
346 |
0 |
0 |
T205 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
143 |
133 |
0 |
0 |
T41 |
24 |
23 |
0 |
0 |
T42 |
13 |
12 |
0 |
0 |
T43 |
11 |
10 |
0 |
0 |
T48 |
14 |
13 |
0 |
0 |
T195 |
31 |
30 |
0 |
0 |
T196 |
12 |
11 |
0 |
0 |
T197 |
12 |
11 |
0 |
0 |
T198 |
2 |
1 |
0 |
0 |
T199 |
12 |
11 |
0 |
0 |
T200 |
12 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T23,T27,T28 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T25,T41,T42 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T23,T27,T28 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
78 |
61 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T27 |
3 |
2 |
0 |
0 |
T28 |
3 |
2 |
0 |
0 |
T41 |
7 |
6 |
0 |
0 |
T42 |
7 |
6 |
0 |
0 |
T48 |
12 |
11 |
0 |
0 |
T195 |
11 |
10 |
0 |
0 |
T196 |
0 |
6 |
0 |
0 |
T197 |
0 |
2 |
0 |
0 |
T203 |
3 |
2 |
0 |
0 |
T204 |
3 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114 |
103 |
0 |
0 |
T41 |
19 |
18 |
0 |
0 |
T42 |
12 |
11 |
0 |
0 |
T43 |
8 |
7 |
0 |
0 |
T48 |
10 |
9 |
0 |
0 |
T195 |
21 |
20 |
0 |
0 |
T196 |
5 |
4 |
0 |
0 |
T197 |
12 |
11 |
0 |
0 |
T198 |
5 |
4 |
0 |
0 |
T199 |
12 |
11 |
0 |
0 |
T200 |
9 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T45,T46,T47 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T26,T27,T28 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1784 |
1768 |
0 |
0 |
selKnown1 |
531 |
518 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1784 |
1768 |
0 |
0 |
T27 |
356 |
355 |
0 |
0 |
T28 |
310 |
309 |
0 |
0 |
T41 |
9 |
8 |
0 |
0 |
T42 |
6 |
5 |
0 |
0 |
T43 |
3 |
2 |
0 |
0 |
T48 |
16 |
15 |
0 |
0 |
T195 |
16 |
15 |
0 |
0 |
T196 |
0 |
20 |
0 |
0 |
T203 |
650 |
649 |
0 |
0 |
T204 |
346 |
345 |
0 |
0 |
T205 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
531 |
518 |
0 |
0 |
T41 |
14 |
13 |
0 |
0 |
T42 |
13 |
12 |
0 |
0 |
T43 |
15 |
14 |
0 |
0 |
T45 |
115 |
114 |
0 |
0 |
T46 |
131 |
130 |
0 |
0 |
T47 |
164 |
163 |
0 |
0 |
T48 |
10 |
9 |
0 |
0 |
T195 |
23 |
22 |
0 |
0 |
T196 |
12 |
11 |
0 |
0 |
T197 |
6 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T27,T28,T203 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T45,T46,T24 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T27,T28,T203 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
69 |
54 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T27 |
3 |
2 |
0 |
0 |
T28 |
3 |
2 |
0 |
0 |
T41 |
3 |
2 |
0 |
0 |
T42 |
5 |
4 |
0 |
0 |
T43 |
5 |
4 |
0 |
0 |
T48 |
6 |
5 |
0 |
0 |
T195 |
4 |
3 |
0 |
0 |
T196 |
0 |
4 |
0 |
0 |
T203 |
3 |
2 |
0 |
0 |
T204 |
3 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
96 |
82 |
0 |
0 |
T41 |
10 |
9 |
0 |
0 |
T42 |
7 |
6 |
0 |
0 |
T43 |
10 |
9 |
0 |
0 |
T48 |
10 |
9 |
0 |
0 |
T195 |
16 |
15 |
0 |
0 |
T196 |
10 |
9 |
0 |
0 |
T197 |
5 |
4 |
0 |
0 |
T198 |
6 |
5 |
0 |
0 |
T199 |
8 |
7 |
0 |
0 |
T200 |
10 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T45,T70,T9 |
0 | 1 | Covered | T23,T45,T46 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T45,T26,T27 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T45,T70,T9 |
1 | 1 | Covered | T23,T45,T46 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1801 |
1781 |
0 |
0 |
selKnown1 |
1276 |
1249 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1801 |
1781 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T41 |
27 |
26 |
0 |
0 |
T42 |
0 |
13 |
0 |
0 |
T43 |
0 |
15 |
0 |
0 |
T45 |
546 |
545 |
0 |
0 |
T46 |
546 |
545 |
0 |
0 |
T47 |
546 |
545 |
0 |
0 |
T48 |
0 |
17 |
0 |
0 |
T70 |
1 |
0 |
0 |
0 |
T81 |
1 |
0 |
0 |
0 |
T195 |
0 |
10 |
0 |
0 |
T196 |
0 |
31 |
0 |
0 |
T197 |
0 |
3 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
T207 |
1 |
0 |
0 |
0 |
T208 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1276 |
1249 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T27 |
168 |
167 |
0 |
0 |
T28 |
165 |
164 |
0 |
0 |
T41 |
0 |
4 |
0 |
0 |
T42 |
0 |
8 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
0 |
16 |
0 |
0 |
T195 |
0 |
14 |
0 |
0 |
T196 |
0 |
14 |
0 |
0 |
T203 |
641 |
640 |
0 |
0 |
T204 |
181 |
180 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
T207 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T45,T70,T9 |
0 | 1 | Covered | T23,T45,T46 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T45,T26,T27 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T45,T70,T9 |
1 | 1 | Covered | T23,T45,T46 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1804 |
1784 |
0 |
0 |
selKnown1 |
1265 |
1238 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1804 |
1784 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T41 |
26 |
25 |
0 |
0 |
T42 |
0 |
13 |
0 |
0 |
T43 |
0 |
17 |
0 |
0 |
T45 |
546 |
545 |
0 |
0 |
T46 |
546 |
545 |
0 |
0 |
T47 |
546 |
545 |
0 |
0 |
T48 |
0 |
17 |
0 |
0 |
T70 |
1 |
0 |
0 |
0 |
T81 |
1 |
0 |
0 |
0 |
T195 |
0 |
9 |
0 |
0 |
T196 |
0 |
32 |
0 |
0 |
T197 |
0 |
3 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
T207 |
1 |
0 |
0 |
0 |
T208 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1265 |
1238 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T27 |
168 |
167 |
0 |
0 |
T28 |
165 |
164 |
0 |
0 |
T41 |
0 |
4 |
0 |
0 |
T42 |
0 |
7 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
0 |
12 |
0 |
0 |
T195 |
0 |
10 |
0 |
0 |
T196 |
0 |
14 |
0 |
0 |
T203 |
641 |
640 |
0 |
0 |
T204 |
181 |
180 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
T207 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T23,T45,T70 |
0 | 1 | Covered | T23,T45,T26 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T45,T26,T27 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T23,T45,T70 |
1 | 1 | Covered | T23,T45,T26 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
208 |
181 |
0 |
0 |
selKnown1 |
1285 |
1258 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
208 |
181 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T41 |
0 |
9 |
0 |
0 |
T42 |
0 |
20 |
0 |
0 |
T43 |
0 |
8 |
0 |
0 |
T45 |
2 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T48 |
0 |
26 |
0 |
0 |
T70 |
1 |
0 |
0 |
0 |
T81 |
1 |
0 |
0 |
0 |
T195 |
0 |
17 |
0 |
0 |
T196 |
0 |
19 |
0 |
0 |
T197 |
0 |
19 |
0 |
0 |
T203 |
1 |
0 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
T207 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1285 |
1258 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T27 |
176 |
175 |
0 |
0 |
T28 |
156 |
155 |
0 |
0 |
T41 |
0 |
6 |
0 |
0 |
T42 |
0 |
8 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
0 |
13 |
0 |
0 |
T195 |
0 |
14 |
0 |
0 |
T196 |
0 |
15 |
0 |
0 |
T203 |
650 |
649 |
0 |
0 |
T204 |
180 |
179 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
T207 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T23,T45,T70 |
0 | 1 | Covered | T23,T45,T26 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T45,T26,T27 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T23,T45,T70 |
1 | 1 | Covered | T23,T45,T26 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
208 |
181 |
0 |
0 |
selKnown1 |
1282 |
1255 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
208 |
181 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T41 |
0 |
9 |
0 |
0 |
T42 |
0 |
19 |
0 |
0 |
T43 |
0 |
8 |
0 |
0 |
T45 |
2 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T48 |
0 |
25 |
0 |
0 |
T70 |
1 |
0 |
0 |
0 |
T81 |
1 |
0 |
0 |
0 |
T195 |
0 |
19 |
0 |
0 |
T196 |
0 |
19 |
0 |
0 |
T197 |
0 |
17 |
0 |
0 |
T203 |
1 |
0 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
T207 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1282 |
1255 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T27 |
176 |
175 |
0 |
0 |
T28 |
156 |
155 |
0 |
0 |
T41 |
0 |
6 |
0 |
0 |
T42 |
0 |
7 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
0 |
12 |
0 |
0 |
T195 |
0 |
14 |
0 |
0 |
T196 |
0 |
13 |
0 |
0 |
T203 |
650 |
649 |
0 |
0 |
T204 |
180 |
179 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
T207 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T23,T70,T9 |
0 | 1 | Covered | T23,T24,T41 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T23,T27,T28 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T23,T70,T9 |
1 | 1 | Covered | T23,T24,T41 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
195 |
177 |
0 |
0 |
selKnown1 |
27472 |
27442 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
195 |
177 |
0 |
0 |
T41 |
28 |
27 |
0 |
0 |
T42 |
16 |
15 |
0 |
0 |
T43 |
33 |
32 |
0 |
0 |
T48 |
15 |
14 |
0 |
0 |
T195 |
31 |
30 |
0 |
0 |
T196 |
12 |
11 |
0 |
0 |
T197 |
21 |
20 |
0 |
0 |
T198 |
5 |
4 |
0 |
0 |
T199 |
13 |
12 |
0 |
0 |
T200 |
13 |
12 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27472 |
27442 |
0 |
0 |
T26 |
18 |
17 |
0 |
0 |
T27 |
382 |
381 |
0 |
0 |
T28 |
354 |
353 |
0 |
0 |
T52 |
20 |
19 |
0 |
0 |
T53 |
20 |
19 |
0 |
0 |
T54 |
20 |
19 |
0 |
0 |
T155 |
1417 |
1416 |
0 |
0 |
T156 |
1655 |
1654 |
0 |
0 |
T203 |
656 |
655 |
0 |
0 |
T209 |
2342 |
2341 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T23,T70,T9 |
0 | 1 | Covered | T23,T24,T41 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T23,T27,T28 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T23,T70,T9 |
1 | 1 | Covered | T23,T24,T41 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
197 |
179 |
0 |
0 |
selKnown1 |
27475 |
27445 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
197 |
179 |
0 |
0 |
T41 |
31 |
30 |
0 |
0 |
T42 |
16 |
15 |
0 |
0 |
T43 |
29 |
28 |
0 |
0 |
T48 |
15 |
14 |
0 |
0 |
T195 |
33 |
32 |
0 |
0 |
T196 |
13 |
12 |
0 |
0 |
T197 |
20 |
19 |
0 |
0 |
T198 |
5 |
4 |
0 |
0 |
T199 |
13 |
12 |
0 |
0 |
T200 |
14 |
13 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27475 |
27445 |
0 |
0 |
T26 |
18 |
17 |
0 |
0 |
T27 |
382 |
381 |
0 |
0 |
T28 |
354 |
353 |
0 |
0 |
T52 |
20 |
19 |
0 |
0 |
T53 |
20 |
19 |
0 |
0 |
T54 |
20 |
19 |
0 |
0 |
T155 |
1417 |
1416 |
0 |
0 |
T156 |
1655 |
1654 |
0 |
0 |
T203 |
656 |
655 |
0 |
0 |
T209 |
2342 |
2341 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T34,T23,T35 |
0 | 1 | Covered | T34,T23,T35 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T23,T27,T28 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T34,T23,T35 |
1 | 1 | Covered | T34,T23,T35 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
718 |
676 |
0 |
0 |
selKnown1 |
27496 |
27466 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
718 |
676 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T34 |
8 |
7 |
0 |
0 |
T35 |
8 |
7 |
0 |
0 |
T45 |
109 |
108 |
0 |
0 |
T46 |
0 |
127 |
0 |
0 |
T70 |
1 |
0 |
0 |
0 |
T210 |
2 |
1 |
0 |
0 |
T211 |
33 |
32 |
0 |
0 |
T212 |
29 |
28 |
0 |
0 |
T213 |
0 |
1 |
0 |
0 |
T214 |
0 |
1 |
0 |
0 |
T215 |
0 |
24 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27496 |
27466 |
0 |
0 |
T23 |
2 |
1 |
0 |
0 |
T26 |
18 |
17 |
0 |
0 |
T27 |
388 |
387 |
0 |
0 |
T28 |
345 |
344 |
0 |
0 |
T52 |
20 |
19 |
0 |
0 |
T53 |
20 |
19 |
0 |
0 |
T54 |
20 |
19 |
0 |
0 |
T155 |
1417 |
1416 |
0 |
0 |
T203 |
666 |
665 |
0 |
0 |
T209 |
2342 |
2341 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T34,T23,T35 |
0 | 1 | Covered | T34,T23,T35 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T23,T27,T28 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T34,T23,T35 |
1 | 1 | Covered | T34,T23,T35 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
714 |
672 |
0 |
0 |
selKnown1 |
27503 |
27473 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
714 |
672 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T34 |
8 |
7 |
0 |
0 |
T35 |
8 |
7 |
0 |
0 |
T45 |
109 |
108 |
0 |
0 |
T46 |
0 |
127 |
0 |
0 |
T70 |
1 |
0 |
0 |
0 |
T210 |
2 |
1 |
0 |
0 |
T211 |
33 |
32 |
0 |
0 |
T212 |
29 |
28 |
0 |
0 |
T213 |
0 |
1 |
0 |
0 |
T214 |
0 |
1 |
0 |
0 |
T215 |
0 |
24 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27503 |
27473 |
0 |
0 |
T23 |
2 |
1 |
0 |
0 |
T26 |
18 |
17 |
0 |
0 |
T27 |
388 |
387 |
0 |
0 |
T28 |
345 |
344 |
0 |
0 |
T52 |
20 |
19 |
0 |
0 |
T53 |
20 |
19 |
0 |
0 |
T54 |
20 |
19 |
0 |
0 |
T155 |
1417 |
1416 |
0 |
0 |
T203 |
666 |
665 |
0 |
0 |
T209 |
2342 |
2341 |
0 |
0 |