Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T185,T187,T9
0	1	Covered	T185,T187,T9
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T187,T300
1	Covered	T185,T187,T9

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T187,T300
1	Covered	T185,T187,T9

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T185,T187,T9
1	1	Covered	T185,T187,T300

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T187,T9
1	0	Covered	T185,T187,T300
1	1	Covered	T185,T187,T9

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T185,T187,T9

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T187,T9
0	Covered	T185,T187,T300

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T187,T9
0	Covered	T185,T187,T300

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	951128538	934280086	0	0
CheckNGreaterZero_A	1972	1972	0	0
GntImpliesReady_A	951128538	8366	0	0
GntImpliesValid_A	951128538	8366	0	0
GrantKnown_A	951128538	934280086	0	0
IdxKnown_A	951128538	934280086	0	0
IndexIsCorrect_A	951128538	8366	0	0
NoReadyValidNoGrant_A	951128538	0	0	0
Priority_A	951128538	8366	0	0
ReadyAndValidImplyGrant_A	951128538	8366	0	0
ReqAndReadyImplyGrant_A	951128538	8366	0	0
ReqImpliesValid_A	951128538	8366	0	0
ValidKnown_A	951128538	934280086	0	0
gen_data_port_assertion.DataFlow_A	951128538	8366	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	934280086	0	0
T4	813388	813068	0	0
T5	145324	145200	0	0
T6	204182	204080	0	0
T17	440058	439826	0	0
T18	461558	461326	0	0
T34	323840	323738	0	0
T44	317404	317176	0	0
T55	269744	269732	0	0
T64	412816	412590	0	0
T87	933800	933684	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1972	1972	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T34	2	2	0	0
T44	2	2	0	0
T55	2	2	0	0
T64	2	2	0	0
T87	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	8366	0	0
T118	401168	0	0	0
T125	660242	0	0	0
T185	170092	2787	0	0
T187	0	2795	0	0
T226	206618	0	0	0
T263	1222486	0	0	0
T264	317548	0	0	0
T286	278918	0	0	0
T300	0	2784	0	0
T303	184112	0	0	0
T304	201252	0	0	0
T305	189852	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	8366	0	0
T118	401168	0	0	0
T125	660242	0	0	0
T185	170092	2787	0	0
T187	0	2795	0	0
T226	206618	0	0	0
T263	1222486	0	0	0
T264	317548	0	0	0
T286	278918	0	0	0
T300	0	2784	0	0
T303	184112	0	0	0
T304	201252	0	0	0
T305	189852	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	934280086	0	0
T4	813388	813068	0	0
T5	145324	145200	0	0
T6	204182	204080	0	0
T17	440058	439826	0	0
T18	461558	461326	0	0
T34	323840	323738	0	0
T44	317404	317176	0	0
T55	269744	269732	0	0
T64	412816	412590	0	0
T87	933800	933684	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	934280086	0	0
T4	813388	813068	0	0
T5	145324	145200	0	0
T6	204182	204080	0	0
T17	440058	439826	0	0
T18	461558	461326	0	0
T34	323840	323738	0	0
T44	317404	317176	0	0
T55	269744	269732	0	0
T64	412816	412590	0	0
T87	933800	933684	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	8366	0	0
T118	401168	0	0	0
T125	660242	0	0	0
T185	170092	2787	0	0
T187	0	2795	0	0
T226	206618	0	0	0
T263	1222486	0	0	0
T264	317548	0	0	0
T286	278918	0	0	0
T300	0	2784	0	0
T303	184112	0	0	0
T304	201252	0	0	0
T305	189852	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	8366	0	0
T118	401168	0	0	0
T125	660242	0	0	0
T185	170092	2787	0	0
T187	0	2795	0	0
T226	206618	0	0	0
T263	1222486	0	0	0
T264	317548	0	0	0
T286	278918	0	0	0
T300	0	2784	0	0
T303	184112	0	0	0
T304	201252	0	0	0
T305	189852	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	8366	0	0
T118	401168	0	0	0
T125	660242	0	0	0
T185	170092	2787	0	0
T187	0	2795	0	0
T226	206618	0	0	0
T263	1222486	0	0	0
T264	317548	0	0	0
T286	278918	0	0	0
T300	0	2784	0	0
T303	184112	0	0	0
T304	201252	0	0	0
T305	189852	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	8366	0	0
T118	401168	0	0	0
T125	660242	0	0	0
T185	170092	2787	0	0
T187	0	2795	0	0
T226	206618	0	0	0
T263	1222486	0	0	0
T264	317548	0	0	0
T286	278918	0	0	0
T300	0	2784	0	0
T303	184112	0	0	0
T304	201252	0	0	0
T305	189852	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	8366	0	0
T118	401168	0	0	0
T125	660242	0	0	0
T185	170092	2787	0	0
T187	0	2795	0	0
T226	206618	0	0	0
T263	1222486	0	0	0
T264	317548	0	0	0
T286	278918	0	0	0
T300	0	2784	0	0
T303	184112	0	0	0
T304	201252	0	0	0
T305	189852	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	934280086	0	0
T4	813388	813068	0	0
T5	145324	145200	0	0
T6	204182	204080	0	0
T17	440058	439826	0	0
T18	461558	461326	0	0
T34	323840	323738	0	0
T44	317404	317176	0	0
T55	269744	269732	0	0
T64	412816	412590	0	0
T87	933800	933684	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951128538	8366	0	0
T118	401168	0	0	0
T125	660242	0	0	0
T185	170092	2787	0	0
T187	0	2795	0	0
T226	206618	0	0	0
T263	1222486	0	0	0
T264	317548	0	0	0
T286	278918	0	0	0
T300	0	2784	0	0
T303	184112	0	0	0
T304	201252	0	0	0
T305	189852	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T185,T187,T9
0	1	Covered	T185,T187,T300
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T187,T300
1	Covered	T185,T187,T9

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T187,T300
1	Covered	T185,T187,T9

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T185,T187,T300
1	1	Covered	T185,T187,T300

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T187,T9
1	0	Covered	T185,T187,T300
1	1	Covered	T185,T187,T300

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T185,T187,T300

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T187,T9
0	Covered	T185,T187,T300

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T187,T9
0	Covered	T185,T187,T300

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	475564269	467140043	0	0
CheckNGreaterZero_A	986	986	0	0
GntImpliesReady_A	475564269	5178	0	0
GntImpliesValid_A	475564269	5178	0	0
GrantKnown_A	475564269	467140043	0	0
IdxKnown_A	475564269	467140043	0	0
IndexIsCorrect_A	475564269	5178	0	0
NoReadyValidNoGrant_A	475564269	0	0	0
Priority_A	475564269	5178	0	0
ReadyAndValidImplyGrant_A	475564269	5178	0	0
ReqAndReadyImplyGrant_A	475564269	5178	0	0
ReqImpliesValid_A	475564269	5178	0	0
ValidKnown_A	475564269	467140043	0	0
gen_data_port_assertion.DataFlow_A	475564269	5178	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	467140043	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	986	986	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T55	1	1	0	0
T64	1	1	0	0
T87	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	5178	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1724	0	0
T187	0	1732	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1722	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	5178	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1724	0	0
T187	0	1732	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1722	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	467140043	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	467140043	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	5178	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1724	0	0
T187	0	1732	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1722	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	5178	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1724	0	0
T187	0	1732	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1722	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	5178	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1724	0	0
T187	0	1732	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1722	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	5178	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1724	0	0
T187	0	1732	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1722	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	5178	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1724	0	0
T187	0	1732	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1722	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	467140043	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	5178	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1724	0	0
T187	0	1732	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1722	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T185,T187,T9
0	1	Covered	T185,T187,T9
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T187,T300
1	Covered	T185,T187,T9

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T187,T300
1	Covered	T185,T187,T9

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T185,T187,T9
1	1	Covered	T185,T187,T300

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T187,T9
1	0	Covered	T185,T187,T300
1	1	Covered	T185,T187,T9

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T185,T187,T9

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T187,T9
0	Covered	T185,T187,T300

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T187,T9
0	Covered	T185,T187,T300

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	475564269	467140043	0	0
CheckNGreaterZero_A	986	986	0	0
GntImpliesReady_A	475564269	3188	0	0
GntImpliesValid_A	475564269	3188	0	0
GrantKnown_A	475564269	467140043	0	0
IdxKnown_A	475564269	467140043	0	0
IndexIsCorrect_A	475564269	3188	0	0
NoReadyValidNoGrant_A	475564269	0	0	0
Priority_A	475564269	3188	0	0
ReadyAndValidImplyGrant_A	475564269	3188	0	0
ReqAndReadyImplyGrant_A	475564269	3188	0	0
ReqImpliesValid_A	475564269	3188	0	0
ValidKnown_A	475564269	467140043	0	0
gen_data_port_assertion.DataFlow_A	475564269	3188	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	467140043	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	986	986	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T55	1	1	0	0
T64	1	1	0	0
T87	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	3188	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1063	0	0
T187	0	1063	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1062	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	3188	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1063	0	0
T187	0	1063	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1062	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	467140043	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	467140043	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	3188	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1063	0	0
T187	0	1063	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1062	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	3188	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1063	0	0
T187	0	1063	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1062	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	3188	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1063	0	0
T187	0	1063	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1062	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	3188	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1063	0	0
T187	0	1063	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1062	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	3188	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1063	0	0
T187	0	1063	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1062	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	467140043	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	3188	0	0
T118	200584	0	0	0
T125	330121	0	0	0
T185	85046	1063	0	0
T187	0	1063	0	0
T226	103309	0	0	0
T263	611243	0	0	0
T264	158774	0	0	0
T286	139459	0	0	0
T300	0	1062	0	0
T303	92056	0	0	0
T304	100626	0	0	0
T305	94926	0	0	0