Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3830607	1			T72	3075		T73	84		T74	101
values[2]	758836	1			T72	847		T73	51		T74	50
values[3]	110327	1			T72	30		T73	4		T74	2
values[4]	59758	1			T72	8		T74	1		T248	22
values[5]	40671	1			T72	4		T74	1		T248	6
values[6]	29847	1			T248	4		T725	12		T447	15
values[7]	23868	1			T248	4		T725	8		T447	16
values[8]	20535	1			T248	12		T725	7		T447	15
values[9]	18574	1			T248	12		T725	2		T447	16
values[10]	17021	1			T248	6		T725	1		T447	15
values[11]	15860	1			T248	7		T725	5		T447	15
values[12]	14806	1			T248	20		T725	2		T447	15
values[13]	13990	1			T248	10		T725	3		T447	15
values[14]	13227	1			T248	8		T725	1		T447	15
values[15]	12676	1			T248	3		T725	6		T447	15
values[16]	12669	1			T248	4		T725	10		T447	15
values[17]	12294	1			T248	2		T725	9		T447	15
values[18]	11335	1			T248	2		T725	9		T447	15
values[19]	11120	1			T248	4		T725	5		T447	16
values[20]	10862	1			T248	7		T725	5		T447	15
values[21]	10779	1			T248	17		T725	4		T447	15
values[22]	10002	1			T248	20		T725	1		T447	15
values[23]	9619	1			T248	7		T725	1		T447	15
values[24]	9220	1			T248	3		T725	1		T447	15
values[25]	8935	1			T248	2		T725	3		T447	15
values[26]	8754	1			T248	6		T725	18		T447	16
values[27]	8412	1			T248	9		T725	30		T447	15
values[28]	8015	1			T248	2		T725	13		T447	15
values[29]	7655	1			T725	6		T447	16		T452	3
values[30]	7262	1			T447	15		T452	3		T537	16
values[31]	6522	1			T447	15		T452	8		T537	16
values[32]	6103	1			T447	16		T452	11		T537	15
values[33]	5690	1			T447	15		T452	12		T537	15
values[34]	5316	1			T447	15		T452	13		T537	15
values[35]	4964	1			T447	15		T452	15		T537	16
values[36]	4592	1			T447	16		T452	8		T537	15
values[37]	4439	1			T447	15		T452	11		T537	15
values[38]	4274	1			T447	15		T452	9		T537	15
values[39]	4094	1			T447	16		T452	6		T537	15
values[40]	3963	1			T447	15		T452	8		T537	15
values[41]	3856	1			T447	15		T452	5		T537	15
values[42]	3886	1			T447	15		T452	4		T537	15
values[43]	3764	1			T447	15		T452	7		T537	16
values[44]	3645	1			T447	16		T452	5		T537	15
values[45]	3546	1			T447	15		T452	4		T537	15
values[46]	3545	1			T447	15		T452	4		T537	15
values[47]	3509	1			T447	15		T452	3		T537	15
values[48]	3386	1			T447	16		T452	6		T537	15
values[49]	3335	1			T447	15		T452	8		T537	15
values[50]	3184	1			T447	15		T452	6		T537	15
values[51]	3166	1			T447	15		T452	5		T537	15
values[52]	3132	1			T447	15		T452	4		T537	16
values[53]	3209	1			T447	15		T452	13		T537	15
values[54]	3086	1			T447	16		T452	7		T537	15
values[55]	2966	1			T447	15		T452	12		T537	16
values[56]	2966	1			T447	16		T452	8		T537	15
values[57]	2866	1			T447	15		T452	5		T537	15
values[58]	2881	1			T447	16		T452	9		T537	15
values[59]	2799	1			T447	15		T452	7		T537	15
values[60]	2880	1			T447	15		T452	10		T537	15
values[61]	3016	1			T447	15		T452	11		T537	15
values[62]	4598	1			T447	15		T452	14		T537	16
values[63]	12420	1			T447	16		T452	37		T537	16
values[64]	252023	1			T447	2830		T452	147		T537	2962

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4943059	1			T72	3706		T73	120		T74	83
values[2]	838481	1			T72	680		T73	37		T74	20
values[3]	88479	1			T72	15		T73	10		T74	6
values[4]	15123	1			T72	4		T74	3		T80	3
values[5]	5810	1			T79	1		T725	11		T538	1
values[6]	3471	1			T725	11		T538	1		T447	8
values[7]	2657	1			T725	8		T538	1		T447	4
values[8]	2349	1			T725	12		T447	2		T452	1
values[9]	2024	1			T725	1		T447	2		T452	6
values[10]	1768	1			T725	1		T447	2		T452	3
values[11]	1685	1			T725	2		T447	1		T452	3
values[12]	1555	1			T725	3		T447	1		T452	2
values[13]	1392	1			T725	2		T447	1		T452	1
values[14]	1309	1			T725	10		T447	1		T452	1
values[15]	1199	1			T725	6		T447	1		T452	1
values[16]	1143	1			T725	4		T447	1		T452	3
values[17]	1096	1			T725	10		T447	1		T452	2
values[18]	1089	1			T725	11		T447	1		T452	1
values[19]	948	1			T725	9		T447	1		T452	1
values[20]	966	1			T725	19		T447	1		T452	3
values[21]	962	1			T725	5		T447	1		T452	3
values[22]	953	1			T725	1		T447	1		T452	1
values[23]	846	1			T725	2		T447	1		T452	2
values[24]	773	1			T725	4		T447	1		T452	2
values[25]	737	1			T725	3		T447	1		T452	1
values[26]	719	1			T725	4		T447	1		T452	3
values[27]	704	1			T725	4		T447	1		T452	1
values[28]	634	1			T725	3		T447	1		T452	1
values[29]	635	1			T725	1		T447	1		T452	1
values[30]	608	1			T725	4		T447	1		T452	2
values[31]	566	1			T725	3		T447	1		T452	1
values[32]	558	1			T725	2		T447	1		T452	1
values[33]	575	1			T725	5		T447	1		T452	1
values[34]	534	1			T725	6		T447	1		T452	4
values[35]	566	1			T725	2		T447	1		T452	4
values[36]	568	1			T725	5		T447	1		T452	1
values[37]	547	1			T725	2		T447	1		T452	1
values[38]	511	1			T725	1		T447	1		T452	1
values[39]	496	1			T447	1		T452	5		T537	1
values[40]	490	1			T447	1		T452	3		T537	1
values[41]	544	1			T447	1		T452	3		T537	1
values[42]	486	1			T447	1		T452	2		T537	1
values[43]	488	1			T447	1		T452	2		T537	1
values[44]	525	1			T447	1		T452	2		T537	1
values[45]	485	1			T447	1		T452	3		T537	1
values[46]	488	1			T447	1		T452	1		T537	1
values[47]	438	1			T447	1		T452	3		T537	1
values[48]	449	1			T447	1		T452	1		T537	1
values[49]	460	1			T447	1		T452	4		T537	1
values[50]	458	1			T447	1		T452	3		T537	1
values[51]	444	1			T447	1		T452	1		T537	1
values[52]	436	1			T447	1		T452	2		T537	1
values[53]	445	1			T447	1		T452	1		T537	1
values[54]	422	1			T447	1		T452	1		T537	1
values[55]	419	1			T447	1		T452	1		T537	1
values[56]	441	1			T447	1		T452	2		T537	1
values[57]	417	1			T447	1		T452	1		T537	1
values[58]	401	1			T447	1		T452	3		T537	1
values[59]	393	1			T447	1		T452	1		T537	1
values[60]	408	1			T447	1		T452	1		T537	1
values[61]	466	1			T447	1		T452	2		T537	1
values[62]	731	1			T447	1		T452	4		T537	1
values[63]	2805	1			T447	1		T452	21		T537	1
values[64]	26911	1			T447	174		T452	60		T537	203

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	579259	1			T72	641		T73	2		T74	1
values[2]	2712782	1			T72	2620		T73	26		T74	1
values[3]	1244670	1			T72	790		T73	88		T74	114
values[4]	152611	1			T72	18		T73	8		T74	59
values[5]	80350	1			T73	1		T74	5		T80	9
values[6]	53016	1			T80	3		T248	8		T725	19
values[7]	38882	1			T248	18		T725	17		T447	15
values[8]	30993	1			T248	5		T725	17		T447	15
values[9]	25611	1			T248	1		T725	10		T447	15
values[10]	22159	1			T248	4		T725	13		T447	15
values[11]	19731	1			T248	12		T725	5		T447	15
values[12]	18114	1			T248	9		T725	1		T447	15
values[13]	16859	1			T248	8		T725	2		T447	15
values[14]	15900	1			T248	12		T725	3		T447	15
values[15]	15052	1			T248	5		T725	4		T447	15
values[16]	14770	1			T248	3		T725	5		T447	15
values[17]	14221	1			T248	6		T725	5		T447	15
values[18]	13594	1			T248	11		T725	6		T447	16
values[19]	13113	1			T248	18		T725	2		T447	15
values[20]	12578	1			T248	11		T725	6		T447	15
values[21]	12452	1			T248	1		T725	17		T447	15
values[22]	11978	1			T248	2		T725	27		T447	15
values[23]	11190	1			T248	5		T725	13		T447	15
values[24]	10789	1			T248	6		T725	12		T447	15
values[25]	10299	1			T248	7		T725	9		T447	16
values[26]	9646	1			T248	3		T725	4		T447	15
values[27]	9099	1			T248	5		T725	6		T447	15
values[28]	8805	1			T248	12		T725	1		T447	16
values[29]	8317	1			T248	7		T725	1		T447	15
values[30]	7796	1			T248	1		T725	1		T447	15
values[31]	7342	1			T248	3		T725	2		T447	15
values[32]	7024	1			T248	1		T725	3		T447	15
values[33]	6450	1			T248	3		T725	2		T447	15
values[34]	5796	1			T248	1		T725	1		T447	15
values[35]	5352	1			T248	1		T447	15		T452	4
values[36]	5175	1			T248	1		T447	15		T452	9
values[37]	4807	1			T248	2		T447	15		T452	4
values[38]	4677	1			T248	4		T447	15		T452	8
values[39]	4582	1			T248	8		T447	15		T452	7
values[40]	4404	1			T248	5		T447	16		T452	8
values[41]	4258	1			T248	1		T447	16		T452	7
values[42]	4124	1			T248	2		T447	15		T452	6
values[43]	4124	1			T248	2		T447	16		T452	12
values[44]	3934	1			T248	8		T447	15		T452	5
values[45]	3792	1			T248	1		T447	16		T452	9
values[46]	3734	1			T447	16		T452	5		T516	2
values[47]	3794	1			T447	15		T452	7		T537	16
values[48]	3730	1			T447	15		T452	9		T537	15
values[49]	3658	1			T447	15		T452	12		T537	15
values[50]	3677	1			T447	15		T452	21		T537	15
values[51]	3613	1			T447	15		T452	18		T537	15
values[52]	3409	1			T447	15		T452	5		T537	15
values[53]	3272	1			T447	15		T452	8		T537	15
values[54]	3262	1			T447	15		T452	6		T537	15
values[55]	3186	1			T447	15		T452	12		T537	15
values[56]	3191	1			T447	15		T452	12		T537	15
values[57]	3229	1			T447	17		T452	9		T537	15
values[58]	3097	1			T447	15		T452	5		T537	15
values[59]	2984	1			T447	16		T452	8		T537	16
values[60]	3021	1			T447	16		T452	4		T537	16
values[61]	3228	1			T447	15		T452	10		T537	15
values[62]	4352	1			T447	16		T452	14		T537	15
values[63]	10873	1			T447	28		T452	47		T537	18
values[64]	240968	1			T447	2824		T452	147		T537	2724