Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2288973	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33308709

1

T4

9348

T5

18259

T6

86668

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	24464739	1			T4	3349		T5	8974		T6	62970
values[0x0]	9455795	1			T4	5999		T5	9285		T6	23698
values[0x1]	1677148	1			T4	554		T5	1616		T6	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	700996	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34896686

1

T4

9902

T5

19875

T6

86695

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16564002	1			T4	4952		T5	9938		T6	43349
valid_sources[0x01]	16561852	1			T4	4950		T5	9937		T6	43346
valid_sources[0x02]	41128	1			T377	113		T139	3263		T517	20
valid_sources[0x03]	39520	1			T8	1		T377	98		T139	3065
valid_sources[0x04]	38690	1			T377	61		T139	3064		T517	47
valid_sources[0x05]	40565	1			T195	3		T8	1		T377	77
valid_sources[0x06]	39160	1			T8	1		T377	56		T139	3116
valid_sources[0x07]	40250	1			T377	92		T139	3277		T517	29
valid_sources[0x08]	39891	1			T8	1		T377	68		T139	3166
valid_sources[0x09]	39912	1			T195	6		T194	1		T377	37
valid_sources[0x0a]	39997	1			T8	2		T377	47		T139	3080
valid_sources[0x0b]	39512	1			T377	63		T139	3225		T517	23
valid_sources[0x0c]	40475	1			T8	1		T194	2		T377	76
valid_sources[0x0d]	40910	1			T195	1		T8	1		T377	65
valid_sources[0x0e]	39641	1			T377	97		T139	3245		T517	26
valid_sources[0x0f]	38984	1			T377	70		T139	3092		T517	17
valid_sources[0x10]	40192	1			T195	3		T8	3		T377	89
valid_sources[0x11]	38997	1			T194	1		T377	113		T139	3212
valid_sources[0x12]	39782	1			T8	1		T194	1		T377	110
valid_sources[0x13]	38836	1			T377	68		T139	3089		T517	26
valid_sources[0x14]	39171	1			T78	4		T195	3		T8	2
valid_sources[0x15]	39238	1			T194	1		T377	56		T139	3243
valid_sources[0x16]	41854	1			T194	1		T377	118		T139	3172
valid_sources[0x17]	39937	1			T55	39		T377	99		T139	3228
valid_sources[0x18]	40685	1			T194	1		T377	130		T139	3239
valid_sources[0x19]	38890	1			T194	6		T377	90		T139	3173
valid_sources[0x1a]	39483	1			T195	2		T8	1		T377	176
valid_sources[0x1b]	39614	1			T377	91		T139	3244		T517	32
valid_sources[0x1c]	40235	1			T8	1		T377	86		T139	3206
valid_sources[0x1d]	39315	1			T78	5		T8	1		T194	1
valid_sources[0x1e]	40616	1			T8	2		T377	93		T139	3231
valid_sources[0x1f]	39750	1			T195	1		T8	1		T377	82
valid_sources[0x20]	39961	1			T8	1		T194	1		T377	89

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23658735

1

T4

3349

T5

8974

T6

62970

values[0x0]

all_enables

biggest_size

9415660

1

T4

5999

T5

9285

T6

23698

values[0x1]

all_enables

biggest_size

234314

1

T55

20

T77

15

T78

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2912795	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

460225

1

T72

557

T73

22

T74

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1143098	1			T72	1362		T73	52		T74	60
values[0x0]	1087007	1			T72	1312		T73	44		T74	48
values[0x1]	1142915	1			T72	1290		T73	43		T74	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2255177	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1117843

1

T72

1349

T73

50

T74

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52973	1			T72	63		T74	1		T80	2
valid_sources[0x01]	52896	1			T72	64		T74	3		T80	12
valid_sources[0x02]	53479	1			T72	56		T73	3		T74	1
valid_sources[0x03]	52146	1			T72	87		T74	3		T80	5
valid_sources[0x04]	52865	1			T72	36		T73	3		T74	4
valid_sources[0x05]	53319	1			T72	62		T73	5		T74	3
valid_sources[0x06]	53694	1			T72	63		T74	3		T80	7
valid_sources[0x07]	51961	1			T72	93		T73	11		T74	2
valid_sources[0x08]	53497	1			T72	64		T74	1		T80	3
valid_sources[0x09]	52621	1			T72	45		T73	3		T80	3
valid_sources[0x0a]	52339	1			T72	69		T74	3		T80	1
valid_sources[0x0b]	51715	1			T72	60		T74	2		T80	16
valid_sources[0x0c]	51874	1			T72	51		T73	8		T74	1
valid_sources[0x0d]	53384	1			T72	93		T74	2		T80	3
valid_sources[0x0e]	51997	1			T72	57		T74	4		T80	9
valid_sources[0x0f]	52572	1			T72	93		T74	3		T235	4
valid_sources[0x10]	53050	1			T72	66		T74	3		T80	3
valid_sources[0x11]	51869	1			T72	36		T73	5		T74	4
valid_sources[0x12]	51667	1			T72	92		T73	2		T74	1
valid_sources[0x13]	52138	1			T72	41		T74	2		T80	3
valid_sources[0x14]	53228	1			T72	42		T80	3		T79	1
valid_sources[0x15]	52222	1			T72	66		T73	5		T74	1
valid_sources[0x16]	52318	1			T72	49		T73	2		T74	1
valid_sources[0x17]	53071	1			T72	85		T74	1		T80	6
valid_sources[0x18]	52767	1			T72	70		T74	3		T80	2
valid_sources[0x19]	52977	1			T72	72		T73	3		T74	3
valid_sources[0x1a]	53221	1			T72	48		T73	14		T74	2
valid_sources[0x1b]	52471	1			T72	63		T74	3		T80	4
valid_sources[0x1c]	52906	1			T72	83		T73	7		T80	1
valid_sources[0x1d]	52256	1			T72	56		T73	2		T74	5
valid_sources[0x1e]	52530	1			T72	50		T74	3		T79	1
valid_sources[0x1f]	52256	1			T72	79		T74	5		T80	11
valid_sources[0x20]	51829	1			T72	60		T74	3		T80	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48591

1

T72

58

T73

2

T74

1

values[0x0]

all_enables

biggest_size

363266

1

T72

442

T73

18

T74

15

values[0x1]

all_enables

biggest_size

48368

1

T72

57

T73

2

T74

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3116365	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

507969

1

T72

606

T73

19

T74

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1240905	1			T72	1534		T73	57		T74	38
values[0x0]	1142967	1			T72	1376		T73	58		T74	35
values[0x1]	1240462	1			T72	1495		T73	52		T74	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2391884	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1232450

1

T72

1464

T73

45

T74

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56111	1			T72	48		T80	2		T79	2
valid_sources[0x01]	56009	1			T72	83		T80	1		T79	3
valid_sources[0x02]	56859	1			T72	51		T73	1		T80	2
valid_sources[0x03]	57297	1			T72	65		T73	8		T80	57
valid_sources[0x04]	56430	1			T72	26		T80	12		T247	2
valid_sources[0x05]	57650	1			T72	120		T73	1		T74	5
valid_sources[0x06]	56885	1			T72	53		T73	1		T80	17
valid_sources[0x07]	56538	1			T72	122		T74	2		T80	5
valid_sources[0x08]	56846	1			T72	101		T73	2		T74	5
valid_sources[0x09]	56838	1			T72	40		T74	4		T80	11
valid_sources[0x0a]	56480	1			T72	26		T74	4		T80	6
valid_sources[0x0b]	57036	1			T72	46		T80	4		T79	2
valid_sources[0x0c]	55790	1			T72	55		T74	2		T80	11
valid_sources[0x0d]	56568	1			T72	113		T80	15		T79	1
valid_sources[0x0e]	56313	1			T72	100		T80	1		T235	2
valid_sources[0x0f]	56780	1			T72	93		T73	5		T79	1
valid_sources[0x10]	56913	1			T72	76		T73	1		T80	17
valid_sources[0x11]	55460	1			T72	66		T73	1		T80	15
valid_sources[0x12]	55787	1			T72	89		T73	5		T80	5
valid_sources[0x13]	55700	1			T72	63		T73	5		T80	4
valid_sources[0x14]	57239	1			T72	24		T73	9		T74	4
valid_sources[0x15]	55669	1			T72	60		T73	4		T74	2
valid_sources[0x16]	56562	1			T72	45		T80	12		T79	2
valid_sources[0x17]	57077	1			T72	74		T73	6		T80	2
valid_sources[0x18]	57599	1			T72	96		T73	8		T74	1
valid_sources[0x19]	56507	1			T72	36		T73	1		T80	9
valid_sources[0x1a]	56839	1			T72	25		T73	14		T74	2
valid_sources[0x1b]	57486	1			T72	145		T74	2		T80	12
valid_sources[0x1c]	56762	1			T72	69		T73	2		T80	42
valid_sources[0x1d]	56506	1			T72	65		T80	11		T79	2
valid_sources[0x1e]	55314	1			T72	75		T73	11		T80	4
valid_sources[0x1f]	56987	1			T72	58		T73	4		T80	9
valid_sources[0x20]	56646	1			T72	67		T73	6		T80	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53675

1

T72

59

T73

2

T80

13

values[0x0]

all_enables

biggest_size

401142

1

T72

482

T73

15

T74

15

values[0x1]

all_enables

biggest_size

53152

1

T72

65

T73

2

T74

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2946756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

466969

1

T72

527

T73

22

T74

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1155913	1			T72	1384		T73	42		T74	55
values[0x0]	1102456	1			T72	1274		T73	49		T74	64
values[0x1]	1155356	1			T72	1411		T73	34		T74	61

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2282152	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1131573

1

T72

1358

T73

46

T74

62

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52577	1			T72	70		T73	1		T74	7
valid_sources[0x01]	54045	1			T72	58		T74	2		T80	8
valid_sources[0x02]	53832	1			T72	69		T74	2		T80	11
valid_sources[0x03]	52951	1			T72	120		T73	1		T74	2
valid_sources[0x04]	53753	1			T72	39		T73	1		T74	3
valid_sources[0x05]	53149	1			T72	64		T73	2		T80	25
valid_sources[0x06]	53637	1			T72	89		T74	5		T80	7
valid_sources[0x07]	52671	1			T72	127		T80	7		T79	1
valid_sources[0x08]	52528	1			T72	124		T74	3		T79	2
valid_sources[0x09]	54054	1			T72	40		T73	3		T80	1
valid_sources[0x0a]	53485	1			T72	63		T73	2		T80	17
valid_sources[0x0b]	52984	1			T72	40		T74	2		T80	5
valid_sources[0x0c]	52362	1			T72	39		T74	1		T80	3
valid_sources[0x0d]	53130	1			T72	71		T73	2		T74	8
valid_sources[0x0e]	52649	1			T72	55		T73	6		T80	1
valid_sources[0x0f]	54163	1			T72	107		T73	2		T74	1
valid_sources[0x10]	54041	1			T72	44		T73	15		T74	6
valid_sources[0x11]	52718	1			T72	29		T74	3		T80	4
valid_sources[0x12]	52762	1			T72	85		T74	7		T80	3
valid_sources[0x13]	53745	1			T72	43		T74	9		T80	9
valid_sources[0x14]	54747	1			T72	40		T73	4		T74	1
valid_sources[0x15]	53159	1			T72	87		T74	4		T80	4
valid_sources[0x16]	53185	1			T72	29		T74	1		T80	8
valid_sources[0x17]	53810	1			T72	92		T80	14		T79	1
valid_sources[0x18]	54056	1			T72	87		T73	4		T74	4
valid_sources[0x19]	52325	1			T72	54		T80	10		T79	2
valid_sources[0x1a]	54705	1			T72	52		T73	4		T79	4
valid_sources[0x1b]	52667	1			T72	57		T73	2		T235	2
valid_sources[0x1c]	52746	1			T72	72		T73	2		T74	2
valid_sources[0x1d]	54773	1			T72	33		T74	4		T80	6
valid_sources[0x1e]	53045	1			T72	43		T80	15		T79	1
valid_sources[0x1f]	53827	1			T72	85		T74	12		T80	3
valid_sources[0x20]	53428	1			T72	55		T74	2		T80	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48872

1

T72

54

T73

1

T74

3

values[0x0]

all_enables

biggest_size

369127

1

T72

414

T73

20

T74

23

values[0x1]

all_enables

biggest_size

48970

1

T72

59

T73

1

T74

2