Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478407288	53416223	0	0
DepthKnown_A	478407288	478302165	0	0
RvalidKnown_A	478407288	478302165	0	0
WreadyKnown_A	478407288	478302165	0	0
gen_passthru_fifo.paramCheckPass	994	994	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	53416223	0	0
T4	251635	17346	0	0
T5	289141	38147	0	0
T6	194596	253355	0	0
T17	267143	34993	0	0
T19	853528	413134	0	0
T20	302519	28947	0	0
T42	102547	18681	0	0
T53	917879	112159	0	0
T55	115818	0	0	0
T56	0	31016	0	0
T68	640996	3461	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	478302165	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	478302165	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	478302165	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T68	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478407288	41091952	0	0
DepthKnown_A	478407288	478302165	0	0
RvalidKnown_A	478407288	478302165	0	0
WreadyKnown_A	478407288	478302165	0	0
gen_passthru_fifo.paramCheckPass	994	994	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	41091952	0	0
T4	251635	13361	0	0
T5	289141	28479	0	0
T6	194596	160801	0	0
T17	267143	25428	0	0
T19	853528	210454	0	0
T20	302519	23217	0	0
T42	102547	12553	0	0
T53	917879	94338	0	0
T55	115818	0	0	0
T56	0	23489	0	0
T68	640996	1868	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	478302165	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	478302165	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	478302165	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T68	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478407288	38389355	0	0
DepthKnown_A	478407288	478302165	0	0
RvalidKnown_A	478407288	478302165	0	0
WreadyKnown_A	478407288	478302165	0	0
gen_passthru_fifo.paramCheckPass	994	994	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	38389355	0	0
T4	251635	10154	0	0
T5	289141	20261	0	0
T6	194596	596624	0	0
T17	267143	18129	0	0
T19	853528	38718	0	0
T20	302519	17796	0	0
T42	102547	6316	0	0
T53	917879	135775	0	0
T55	115818	39	0	0
T68	640996	459	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	478302165	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	478302165	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	478302165	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T68	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478407288	33143778	0	0
DepthKnown_A	478407288	478302165	0	0
RvalidKnown_A	478407288	478302165	0	0
WreadyKnown_A	478407288	478302165	0	0
gen_passthru_fifo.paramCheckPass	994	994	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	33143778	0	0
T4	251635	9902	0	0
T5	289141	19875	0	0
T6	194596	86695	0	0
T17	267143	17745	0	0
T19	853528	35567	0	0
T20	302519	17387	0	0
T42	102547	6188	0	0
T53	917879	86199	0	0
T55	115818	39	0	0
T68	640996	351	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	478302165	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	478302165	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	478302165	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T68	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	558412117	89392	0	0
DepthKnown_A	558412117	558294642	0	0
RvalidKnown_A	558412117	558294642	0	0
WreadyKnown_A	558412117	558294642	0	0
gen_passthru_fifo.paramCheckPass	2885	2885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	89392	0	0
T4	251635	29	0	0
T5	289141	151	0	0
T6	194596	29	0	0
T17	267143	151	0	0
T19	853528	98	0	0
T20	302519	49	0	0
T42	102547	13	0	0
T53	917879	34	0	0
T55	115818	0	0	0
T56	0	68	0	0
T68	640996	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T68	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	558412117	92674	0	0
DepthKnown_A	558412117	558294642	0	0
RvalidKnown_A	558412117	558294642	0	0
WreadyKnown_A	558412117	558294642	0	0
gen_passthru_fifo.paramCheckPass	2885	2885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	92674	0	0
T4	251635	29	0	0
T5	289141	151	0	0
T6	194596	29	0	0
T17	267143	151	0	0
T19	853528	98	0	0
T20	302519	49	0	0
T42	102547	13	0	0
T53	917879	34	0	0
T55	115818	0	0	0
T56	0	68	0	0
T68	640996	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T68	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	558412117	50604	0	0
DepthKnown_A	558412117	558294642	0	0
RvalidKnown_A	558412117	558294642	0	0
WreadyKnown_A	558412117	558294642	0	0
gen_passthru_fifo.paramCheckPass	2885	2885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	50604	0	0
T4	251635	25	0	0
T5	289141	95	0	0
T6	194596	0	0	0
T17	267143	95	0	0
T19	853528	98	0	0
T20	302519	46	0	0
T42	102547	12	0	0
T53	917879	5	0	0
T55	115818	0	0	0
T56	0	64	0	0
T68	640996	8	0	0
T111	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T68	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	558412117	50604	0	0
DepthKnown_A	558412117	558294642	0	0
RvalidKnown_A	558412117	558294642	0	0
WreadyKnown_A	558412117	558294642	0	0
gen_passthru_fifo.paramCheckPass	2885	2885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	50604	0	0
T4	251635	25	0	0
T5	289141	95	0	0
T6	194596	0	0	0
T17	267143	95	0	0
T19	853528	98	0	0
T20	302519	46	0	0
T42	102547	12	0	0
T53	917879	5	0	0
T55	115818	0	0	0
T56	0	64	0	0
T68	640996	8	0	0
T111	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T68	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	558412117	38788	0	0
DepthKnown_A	558412117	558294642	0	0
RvalidKnown_A	558412117	558294642	0	0
WreadyKnown_A	558412117	558294642	0	0
gen_passthru_fifo.paramCheckPass	2885	2885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	38788	0	0
T4	251635	4	0	0
T5	289141	56	0	0
T6	194596	29	0	0
T17	267143	56	0	0
T18	0	3	0	0
T19	853528	0	0	0
T20	302519	3	0	0
T42	102547	1	0	0
T53	917879	29	0	0
T55	115818	0	0	0
T56	0	4	0	0
T68	640996	0	0	0
T111	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T68	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	558412117	42070	0	0
DepthKnown_A	558412117	558294642	0	0
RvalidKnown_A	558412117	558294642	0	0
WreadyKnown_A	558412117	558294642	0	0
gen_passthru_fifo.paramCheckPass	2885	2885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	42070	0	0
T4	251635	4	0	0
T5	289141	56	0	0
T6	194596	29	0	0
T17	267143	56	0	0
T18	0	3	0	0
T19	853528	0	0	0
T20	302519	3	0	0
T42	102547	1	0	0
T53	917879	29	0	0
T55	115818	0	0	0
T56	0	4	0	0
T68	640996	0	0	0
T111	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	558294642	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	115807	0	0
T68	640996	640938	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T68	1	1	0	0