Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.26 90.91 69.23 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.90 90.48 72.22 88.89 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.18 94.12 89.29 99.75 100.00 72.73 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_intg_gen 94.12 88.24 100.00
u_rsp_chk 93.33 100.00 80.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.91 91.30 82.35 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.79 95.35 81.82 90.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.18 94.12 89.29 99.75 100.00 72.73 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_intg_gen 100.00 100.00 100.00
u_rsp_chk 93.33 100.00 80.00 100.00

Line Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Line Coverage for Module self-instances :
SCORELINE
90.91 91.30
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Line No.TotalCoveredPercent
TOTAL232191.30
ALWAYS7033100.00
ALWAYS7855100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS1324375.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN149100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
73 1 1
78 1 1
80 1 1
81 1 1
82 1 1
84 1 1
MISSING_ELSE
89 1 1
94 1 1
96 1 1
116 1 1
118 1 1
119 1 1
120 1 1
132 1 1
133 1 1
134 1 1
135 0 1
MISSING_ELSE
141 1 1
145 1 1
149 0 1
153 1 1
168 unreachable
170 unreachable
171 unreachable
172 unreachable
173 unreachable
==> MISSING_ELSE
178 unreachable
179 unreachable
181 unreachable


Line Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Line Coverage for Module self-instances :
SCORELINE
87.26 90.91
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Line No.TotalCoveredPercent
TOTAL222090.91
ALWAYS7033100.00
ALWAYS7855100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS1324375.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN149100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
73 1 1
78 1 1
80 1 1
81 1 1
82 1 1
84 1 1
MISSING_ELSE
89 1 1
94 unreachable
96 1 1
116 1 1
118 1 1
119 1 1
120 1 1
132 1 1
133 1 1
134 1 1
135 0 1
MISSING_ELSE
141 1 1
145 1 1
149 0 1
153 1 1
168 unreachable
170 unreachable
171 unreachable
172 unreachable
173 unreachable
==> MISSING_ELSE
178 unreachable
179 unreachable
181 unreachable


Cond Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Cond Coverage for Module self-instances :
SCORECOND
87.26 69.23
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
            --------------------------------------------1-------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0Unreachable
1CoveredT4,T5,T6

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0Unreachable
1CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0Unreachable
1Unreachable

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10CoveredT17,T106,T209

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10Not Covered

Cond Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Cond Coverage for Module self-instances :
SCORECOND
90.91 82.35
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

TotalCoveredPercent
Conditions171482.35
Logical171482.35
Non-Logical00
Event00

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT55,T77,T78
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10CoveredT17,T147,T106

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10Not Covered

Branch Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
90.91 90.00
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 94 2 2 100.00
IF 132 3 2 66.67
IF 70 2 2 100.00
IF 80 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 94 ((~we_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 132 if ((!rst_ni)) -2-: 134 if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Not Covered
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 70 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 80 if ((req_i && gnt_o)) -2-: 81 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))

Branches:
-1--2-StatusTests
1 1 Covered T4,T5,T6
1 0 Covered T4,T5,T6
0 - Covered T4,T5,T6


Branch Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Branch Coverage for Module self-instances :
SCOREBRANCH
87.26 88.89
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Line No.TotalCoveredPercent
Branches 9 8 88.89
TERNARY 94 1 1 100.00
IF 132 3 2 66.67
IF 70 2 2 100.00
IF 80 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 94 ((~we_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Unreachable


LineNo. Expression -1-: 132 if ((!rst_ni)) -2-: 134 if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Not Covered
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 70 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 80 if ((req_i && gnt_o)) -2-: 81 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))

Branches:
-1--2-StatusTests
1 1 Covered T4,T5,T6
1 0 Covered T4,T5,T6
0 - Covered T4,T5,T6


Assert Coverage for Module : tlul_adapter_host
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 956814576 91767016 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 956814576 91767016 0 0
T4 503270 27500 0 0
T5 578282 58408 0 0
T6 389192 849979 0 0
T17 534286 53122 0 0
T19 1707056 451852 0 0
T20 605038 46743 0 0
T42 205094 24997 0 0
T53 1835758 247934 0 0
T55 231636 0 0 0
T56 0 49280 0 0
T68 1281992 3920 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
Line No.TotalCoveredPercent
TOTAL222090.91
ALWAYS7033100.00
ALWAYS7855100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS1324375.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN149100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
73 1 1
78 1 1
80 1 1
81 1 1
82 1 1
84 1 1
MISSING_ELSE
89 1 1
94 unreachable
96 1 1
116 1 1
118 1 1
119 1 1
120 1 1
132 1 1
133 1 1
134 1 1
135 0 1
MISSING_ELSE
141 1 1
145 1 1
149 0 1
153 1 1
168 unreachable
170 unreachable
171 unreachable
172 unreachable
173 unreachable
==> MISSING_ELSE
178 unreachable
179 unreachable
181 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
            --------------------------------------------1-------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0Unreachable
1CoveredT4,T5,T6

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0Unreachable
1CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0Unreachable
1Unreachable

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10CoveredT17,T106,T209

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
Line No.TotalCoveredPercent
Branches 9 8 88.89
TERNARY 94 1 1 100.00
IF 132 3 2 66.67
IF 70 2 2 100.00
IF 80 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 94 ((~we_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Unreachable


LineNo. Expression -1-: 132 if ((!rst_ni)) -2-: 134 if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Not Covered
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 70 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 80 if ((req_i && gnt_o)) -2-: 81 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))

Branches:
-1--2-StatusTests
1 1 Covered T4,T5,T6
1 0 Covered T4,T5,T6
0 - Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 478407288 53416223 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 478407288 53416223 0 0
T4 251635 17346 0 0
T5 289141 38147 0 0
T6 194596 253355 0 0
T17 267143 34993 0 0
T19 853528 413134 0 0
T20 302519 28947 0 0
T42 102547 18681 0 0
T53 917879 112159 0 0
T55 115818 0 0 0
T56 0 31016 0 0
T68 640996 3461 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
Line No.TotalCoveredPercent
TOTAL232191.30
ALWAYS7033100.00
ALWAYS7855100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS1324375.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN149100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
73 1 1
78 1 1
80 1 1
81 1 1
82 1 1
84 1 1
MISSING_ELSE
89 1 1
94 1 1
96 1 1
116 1 1
118 1 1
119 1 1
120 1 1
132 1 1
133 1 1
134 1 1
135 0 1
MISSING_ELSE
141 1 1
145 1 1
149 0 1
153 1 1
168 unreachable
170 unreachable
171 unreachable
172 unreachable
173 unreachable
==> MISSING_ELSE
178 unreachable
179 unreachable
181 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
TotalCoveredPercent
Conditions171482.35
Logical171482.35
Non-Logical00
Event00

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT55,T77,T78
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10CoveredT17,T147,T106

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 94 2 2 100.00
IF 132 3 2 66.67
IF 70 2 2 100.00
IF 80 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 94 ((~we_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 132 if ((!rst_ni)) -2-: 134 if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Not Covered
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 70 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 80 if ((req_i && gnt_o)) -2-: 81 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))

Branches:
-1--2-StatusTests
1 1 Covered T4,T5,T6
1 0 Covered T4,T5,T6
0 - Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 478407288 38350793 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 478407288 38350793 0 0
T4 251635 10154 0 0
T5 289141 20261 0 0
T6 194596 596624 0 0
T17 267143 18129 0 0
T19 853528 38718 0 0
T20 302519 17796 0 0
T42 102547 6316 0 0
T53 917879 135775 0 0
T55 115818 0 0 0
T56 0 18264 0 0
T68 640996 459 0 0

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