Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sysrst_ctrl_aon 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_sysrst_ctrl_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : sysrst_ctrl
TotalCoveredPercent
Totals 50 50 100.00
Total Bits 334 334 100.00
Total Bits 0->1 167 167 100.00
Total Bits 1->0 167 167 100.00

Ports 50 50 100.00
Port Bits 334 334 100.00
Port Bits 0->1 167 167 100.00
Port Bits 1->0 167 167 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_aon_ni Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T20,T45,T189 Yes T20,T45,T189 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T20,T45,T189 Yes T20,T45,T189 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[7:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[15:8] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[21:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T55,*T75,*T76 Yes T55,T75,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T55,T77,T78 Yes T55,T77,T78 INPUT
tl_i.a_valid Yes Yes T20,T45,T189 Yes T20,T45,T189 INPUT
tl_o.a_ready Yes Yes T20,T45,T189 Yes T20,T45,T189 OUTPUT
tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T20,T45,T189 Yes T20,T45,T189 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T20,T45,T189 Yes T20,T45,T189 OUTPUT
tl_o.d_data[31:0] Yes Yes T20,T45,T189 Yes T20,T45,T189 OUTPUT
tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[5:0] Yes Yes *T78,*T72,*T74 Yes T78,T72,T73 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T20,*T45,*T189 Yes T20,T45,T189 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T20,T45,T189 Yes T20,T45,T189 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T81,T82,T679 Yes T81,T82,T679 INPUT
alert_rx_i[0].ping_n Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[0].ping_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T81,T82,T679 Yes T81,T82,T679 OUTPUT
wkup_req_o Yes Yes T20,T189,T1 Yes T20,T45,T189 OUTPUT
rst_req_o Yes Yes T20,T189,T262 Yes T20,T189,T262 OUTPUT
intr_event_detected_o Yes Yes T319,T199,T200 Yes T319,T199,T200 OUTPUT
cio_ac_present_i Yes Yes T179,T31,T199 Yes T179,T31,T199 INPUT
cio_ec_rst_l_i Yes Yes T179,T31,T32 Yes T179,T31,T32 INPUT
cio_key0_in_i Yes Yes T20,T189,T179 Yes T20,T189,T179 INPUT
cio_key1_in_i Yes Yes T179,T31,T32 Yes T179,T31,T32 INPUT
cio_key2_in_i Yes Yes T179,T31,T199 Yes T179,T31,T199 INPUT
cio_pwrb_in_i Yes Yes T1,T179,T2 Yes T1,T179,T2 INPUT
cio_lid_open_i Yes Yes T45,T179,T46 Yes T45,T179,T46 INPUT
cio_flash_wp_l_i Yes Yes T21,T31,T32 Yes T21,T45,T179 INPUT
cio_bat_disable_o Yes Yes T20,T189,T262 Yes T20,T189,T262 OUTPUT
cio_flash_wp_l_o Yes Yes T31,T32,T33 Yes T45,T46,T31 OUTPUT
cio_ec_rst_l_o Yes Yes T31,T32,T33 Yes T31,T32,T33 OUTPUT
cio_key0_out_o Yes Yes T20,T189,T179 Yes T20,T189,T179 OUTPUT
cio_key1_out_o Yes Yes T179,T31,T32 Yes T179,T31,T32 OUTPUT
cio_key2_out_o Yes Yes T179,T31,T78 Yes T179,T31,T32 OUTPUT
cio_pwrb_out_o Yes Yes T1,T179,T2 Yes T1,T179,T2 OUTPUT
cio_z3_wakeup_o Yes Yes T31,T202,T203 Yes T45,T46,T31 OUTPUT
cio_bat_disable_en_o Unreachable Unreachable Unreachable OUTPUT
cio_flash_wp_l_en_o Unreachable Unreachable Unreachable OUTPUT
cio_ec_rst_l_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key0_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key1_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key2_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pwrb_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_z3_wakeup_en_o Unreachable Unreachable Unreachable OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%