Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : uart
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_uart0 100.00 100.00
tb.dut.top_earlgrey.u_uart1 100.00 100.00
tb.dut.top_earlgrey.u_uart2 100.00 100.00
tb.dut.top_earlgrey.u_uart3 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : uart
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 308 308 100.00
Total Bits 0->1 154 154 100.00
Total Bits 1->0 154 154 100.00

Ports 40 40 100.00
Port Bits 308 308 100.00
Port Bits 0->1 154 154 100.00
Port Bits 1->0 154 154 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T6,T53 Yes T4,T6,T53 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T6,T53 Yes T4,T6,T53 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T55,*T75,*T76 Yes T55,T75,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T55,T77,T78 Yes T55,T77,T78 INPUT
tl_i.a_valid Yes Yes T4,T6,T53 Yes T4,T6,T53 INPUT
tl_o.a_ready Yes Yes T6,T53,T54 Yes T6,T53,T54 OUTPUT
tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T6,T53,T54 Yes T6,T53,T54 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T6,T53,T54 Yes T6,T53,T54 OUTPUT
tl_o.d_data[31:0] Yes Yes T6,T53,T54 Yes T6,T53,T54 OUTPUT
tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T74,*T80 Yes T72,T73,T74 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T6,*T53,*T54 Yes T6,T53,T54 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T6,T53,T54 Yes T6,T53,T54 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T147,T209,T680 Yes T147,T209,T680 INPUT
alert_rx_i[0].ping_n Yes Yes T147,T81,T82 Yes T147,T81,T82 INPUT
alert_rx_i[0].ping_p Yes Yes T147,T81,T82 Yes T147,T81,T82 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T147,T209,T680 Yes T147,T209,T680 OUTPUT
cio_rx_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cio_tx_o Yes Yes T6,T53,T54 Yes T6,T53,T54 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T177,T103,T306 Yes T177,T103,T306 OUTPUT
intr_tx_empty_o Yes Yes T177,T103,T306 Yes T177,T103,T306 OUTPUT
intr_rx_watermark_o Yes Yes T177,T103,T306 Yes T177,T103,T306 OUTPUT
intr_tx_done_o Yes Yes T177,T103,T306 Yes T177,T103,T306 OUTPUT
intr_rx_overflow_o Yes Yes T177,T103,T306 Yes T177,T103,T306 OUTPUT
intr_rx_frame_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_break_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_timeout_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_parity_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 304 304 100.00
Total Bits 0->1 152 152 100.00
Total Bits 1->0 152 152 100.00

Ports 40 40 100.00
Port Bits 304 304 100.00
Port Bits 0->1 152 152 100.00
Port Bits 1->0 152 152 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T6,T53 Yes T4,T6,T53 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T6,T53 Yes T4,T6,T53 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[29:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T55,*T75,*T76 Yes T55,T75,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T55,T77,T78 Yes T55,T77,T78 INPUT
tl_i.a_valid Yes Yes T4,T6,T53 Yes T4,T6,T53 INPUT
tl_o.a_ready Yes Yes T6,T53,T54 Yes T6,T53,T54 OUTPUT
tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T6,T53,T54 Yes T6,T53,T54 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T6,T53,T54 Yes T6,T53,T54 OUTPUT
tl_o.d_data[31:0] Yes Yes T6,T53,T54 Yes T6,T53,T54 OUTPUT
tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T74,*T80 Yes T72,T73,T74 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T6,*T53,*T54 Yes T6,T53,T54 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T6,T53,T54 Yes T6,T53,T54 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T147,T680,T152 Yes T147,T680,T152 INPUT
alert_rx_i[0].ping_n Yes Yes T147,T81,T82 Yes T147,T81,T82 INPUT
alert_rx_i[0].ping_p Yes Yes T147,T81,T82 Yes T147,T81,T82 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T147,T680,T152 Yes T147,T680,T152 OUTPUT
cio_rx_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cio_tx_o Yes Yes T6,T53,T54 Yes T6,T53,T54 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T306,T307,T308 Yes T306,T307,T308 OUTPUT
intr_tx_empty_o Yes Yes T306,T307,T308 Yes T306,T307,T308 OUTPUT
intr_rx_watermark_o Yes Yes T306,T307,T308 Yes T306,T307,T308 OUTPUT
intr_tx_done_o Yes Yes T306,T307,T308 Yes T306,T307,T308 OUTPUT
intr_rx_overflow_o Yes Yes T306,T307,T308 Yes T306,T307,T308 OUTPUT
intr_rx_frame_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_break_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_timeout_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_parity_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 40 40 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T138,T207,T319 Yes T138,T207,T319 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T138,T207,T319 Yes T138,T207,T319 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T55,*T75,*T76 Yes T55,T75,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T55,T77,T78 Yes T55,T77,T78 INPUT
tl_i.a_valid Yes Yes T147,T152,T138 Yes T147,T152,T138 INPUT
tl_o.a_ready Yes Yes T147,T152,T138 Yes T147,T152,T138 OUTPUT
tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T80 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T138,T207,T319 Yes T138,T207,T319 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T147,T152,T138 Yes T147,T152,T138 OUTPUT
tl_o.d_data[31:0] Yes Yes T147,T152,T138 Yes T147,T152,T138 OUTPUT
tl_o.d_sink Yes Yes T72,T74,T80 Yes T72,T74,T80 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T80,*T79 Yes T72,T74,T80 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T74,T79 Yes T72,T74,T80 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T138,*T207,*T319 Yes T138,T207,T319 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T147,T152,T138 Yes T147,T152,T138 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T147,T348,T152 Yes T147,T348,T152 INPUT
alert_rx_i[0].ping_n Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[0].ping_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T147,T348,T152 Yes T147,T348,T152 OUTPUT
cio_rx_i Yes Yes T138,T207,T329 Yes T22,T138,T207 INPUT
cio_tx_o Yes Yes T138,T207,T329 Yes T138,T207,T329 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T138,T207,T319 Yes T138,T207,T319 OUTPUT
intr_tx_empty_o Yes Yes T138,T207,T319 Yes T138,T207,T319 OUTPUT
intr_rx_watermark_o Yes Yes T138,T207,T319 Yes T138,T207,T319 OUTPUT
intr_tx_done_o Yes Yes T138,T207,T319 Yes T138,T207,T319 OUTPUT
intr_rx_overflow_o Yes Yes T138,T207,T319 Yes T138,T207,T319 OUTPUT
intr_rx_frame_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_break_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_timeout_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_parity_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 40 40 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T177,T103,T325 Yes T177,T103,T325 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T177,T103,T325 Yes T177,T103,T325 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[16:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T55,*T75,*T76 Yes T55,T75,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T55,T77,T78 Yes T55,T77,T78 INPUT
tl_i.a_valid Yes Yes T177,T147,T103 Yes T177,T147,T103 INPUT
tl_o.a_ready Yes Yes T177,T147,T103 Yes T177,T147,T103 OUTPUT
tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T177,T103,T325 Yes T177,T103,T325 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T177,T147,T103 Yes T177,T147,T103 OUTPUT
tl_o.d_data[31:0] Yes Yes T177,T147,T103 Yes T177,T147,T103 OUTPUT
tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T80,*T79 Yes T72,T74,T80 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T74,T80 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T177,*T103,*T325 Yes T177,T103,T325 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T177,T147,T103 Yes T177,T147,T103 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T147,T152,T681 Yes T147,T152,T681 INPUT
alert_rx_i[0].ping_n Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[0].ping_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T147,T152,T681 Yes T147,T152,T681 OUTPUT
cio_rx_i Yes Yes T177,T103,T325 Yes T177,T103,T325 INPUT
cio_tx_o Yes Yes T177,T103,T325 Yes T177,T103,T325 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T177,T103,T325 Yes T177,T103,T325 OUTPUT
intr_tx_empty_o Yes Yes T177,T103,T325 Yes T177,T103,T325 OUTPUT
intr_rx_watermark_o Yes Yes T177,T103,T325 Yes T177,T103,T325 OUTPUT
intr_tx_done_o Yes Yes T177,T103,T325 Yes T177,T103,T325 OUTPUT
intr_rx_overflow_o Yes Yes T177,T103,T325 Yes T177,T103,T325 OUTPUT
intr_rx_frame_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_break_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_timeout_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_parity_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 308 308 100.00
Total Bits 0->1 154 154 100.00
Total Bits 1->0 154 154 100.00

Ports 40 40 100.00
Port Bits 308 308 100.00
Port Bits 0->1 154 154 100.00
Port Bits 1->0 154 154 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T28,T29,T316 Yes T28,T29,T316 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T28,T29,T316 Yes T28,T29,T316 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T55,*T75,*T76 Yes T55,T75,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T55,T77,T78 Yes T55,T77,T78 INPUT
tl_i.a_valid Yes Yes T147,T152,T28 Yes T147,T152,T28 INPUT
tl_o.a_ready Yes Yes T147,T152,T28 Yes T147,T152,T28 OUTPUT
tl_o.d_error Yes Yes T72,T73,T80 Yes T72,T73,T80 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T28,T29,T316 Yes T28,T29,T316 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T147,T152,T28 Yes T147,T152,T28 OUTPUT
tl_o.d_data[31:0] Yes Yes T147,T152,T28 Yes T147,T152,T28 OUTPUT
tl_o.d_sink Yes Yes T72,T73,T80 Yes T72,T73,T74 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T80,*T79 Yes T72,T73,T74 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T73,T80 Yes T72,T73,T74 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T28,*T29,*T316 Yes T28,T29,T316 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T147,T152,T28 Yes T147,T152,T28 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T147,T209,T152 Yes T147,T209,T152 INPUT
alert_rx_i[0].ping_n Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[0].ping_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T147,T209,T152 Yes T147,T209,T152 OUTPUT
cio_rx_i Yes Yes T28,T29,T316 Yes T28,T29,T316 INPUT
cio_tx_o Yes Yes T28,T29,T316 Yes T28,T29,T316 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T28,T29,T316 Yes T28,T29,T316 OUTPUT
intr_tx_empty_o Yes Yes T28,T29,T316 Yes T28,T29,T316 OUTPUT
intr_rx_watermark_o Yes Yes T28,T29,T316 Yes T28,T29,T316 OUTPUT
intr_tx_done_o Yes Yes T28,T29,T316 Yes T28,T29,T316 OUTPUT
intr_rx_overflow_o Yes Yes T28,T29,T316 Yes T28,T29,T316 OUTPUT
intr_rx_frame_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_break_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_timeout_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT
intr_rx_parity_err_o Yes Yes T319,T320,T321 Yes T319,T320,T321 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%