Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : entropy_src
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.38 93.38

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_entropy_src_0.1/rtl/entropy_src.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_entropy_src 99.02 99.02



Module Instance : tb.dut.top_earlgrey.u_entropy_src

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : entropy_src
TotalCoveredPercent
Totals 65 54 83.08
Total Bits 1300 1214 93.38
Total Bits 0->1 650 607 93.38
Total Bits 1->0 650 607 93.38

Ports 65 54 83.08
Port Bits 1300 1214 93.38
Port Bits 0->1 650 607 93.38
Port Bits 1->0 650 607 93.38

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[7:0] Yes Yes *T72,*T74,*T80 Yes T72,T74,T80 INPUT
tl_i.a_address[16:8] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:17] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T8,*T72,*T73 Yes T8,T72,T73 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T74,T80 Yes T72,T74,T80 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T119,T120,T121 Yes T119,T120,T121 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_sink Yes Yes T72,T74,T80 Yes T72,T74,T80 OUTPUT
tl_o.d_source[5:0] Yes Yes *T8,*T72,*T80 Yes T8,T72,T73 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T74,T80 Yes T72,T74,T80 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T119,*T120,*T121 Yes T53,T119,T54 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_en_entropy_src_fw_read_i[7:0] Unreachable Unreachable Unreachable INPUT
otp_en_entropy_src_fw_over_i[7:0] Unreachable Unreachable Unreachable INPUT
rng_fips_o Yes Yes T117,T107,T118 Yes T119,T120,T121 OUTPUT
entropy_src_hw_if_i.es_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
entropy_src_hw_if_o.es_fips Yes Yes T107,T118,T109 Yes T119,T120,T121 OUTPUT
entropy_src_hw_if_o.es_bits[383:0] Yes Yes T120,T121,T110 Yes T121,T110,T101 OUTPUT
entropy_src_hw_if_o.es_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_rng_o.rng_enable Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_rng_i.rng_b[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
entropy_src_rng_i.rng_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cs_aes_halt_o.cs_aes_halt_req Yes Yes T119,T120,T121 Yes T119,T120,T121 OUTPUT
cs_aes_halt_i.cs_aes_halt_ack Yes Yes T119,T120,T121 Yes T119,T120,T121 INPUT
entropy_src_xht_o.threshold_scope No No No OUTPUT
entropy_src_xht_o.window_wrap_pulse Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_xht_o.health_test_window[15:0] Yes Yes *T377,*T376,*T140 Yes T377,T376,T140 OUTPUT
entropy_src_xht_o.health_test_window[17:16] No No No OUTPUT
entropy_src_xht_o.thresh_lo[13:0] Yes Yes *T133,*T131,*T132 Yes T133,T131,T132 OUTPUT
entropy_src_xht_o.thresh_lo[14] No No No OUTPUT
entropy_src_xht_o.thresh_lo[15] Yes Yes T127,T133,T131 Yes T127,T133,T131 OUTPUT
entropy_src_xht_o.thresh_hi[15:0] Yes Yes T127,T133,T132 Yes T127,T133,T132 OUTPUT
entropy_src_xht_o.active No No No OUTPUT
entropy_src_xht_o.clear Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_xht_o.rng_bit_sel[1:0] No No No OUTPUT
entropy_src_xht_o.rng_bit_en No No No OUTPUT
entropy_src_xht_o.entropy_bit_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_xht_o.entropy_bit[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_xht_i.test_fail_lo_pulse No No No INPUT
entropy_src_xht_i.test_fail_hi_pulse No No No INPUT
entropy_src_xht_i.continuous_test No No No INPUT
entropy_src_xht_i.test_cnt_lo[15:0] No No No INPUT
entropy_src_xht_i.test_cnt_hi[15:0] No No No INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[0].ping_n Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[0].ping_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[1].ping_n Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[1].ping_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
intr_es_entropy_valid_o Yes Yes T253,T317,T322 Yes T253,T317,T322 OUTPUT
intr_es_health_test_failed_o Yes Yes T253,T317,T322 Yes T253,T317,T322 OUTPUT
intr_es_observe_fifo_ready_o Yes Yes T253,T317,T322 Yes T253,T317,T322 OUTPUT
intr_es_fatal_err_o Yes Yes T253,T317,T322 Yes T253,T317,T322 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_entropy_src
TotalCoveredPercent
Totals 58 54 93.10
Total Bits 1226 1214 99.02
Total Bits 0->1 613 607 99.02
Total Bits 1->0 613 607 99.02

Ports 58 54 93.10
Port Bits 1226 1214 99.02
Port Bits 0->1 613 607 99.02
Port Bits 1->0 613 607 99.02

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[7:0] Yes Yes *T72,*T74,*T80 Yes T72,T74,T80 INPUT
tl_i.a_address[16:8] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:17] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T8,*T72,*T73 Yes T8,T72,T73 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T74,T80 Yes T72,T74,T80 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T119,T120,T121 Yes T119,T120,T121 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_sink Yes Yes T72,T74,T80 Yes T72,T74,T80 OUTPUT
tl_o.d_source[5:0] Yes Yes *T8,*T72,*T80 Yes T8,T72,T73 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T74,T80 Yes T72,T74,T80 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T119,*T120,*T121 Yes T53,T119,T54 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_en_entropy_src_fw_read_i[7:0] Unreachable Unreachable Unreachable INPUT
otp_en_entropy_src_fw_over_i[7:0] Unreachable Unreachable Unreachable INPUT
rng_fips_o Yes Yes T117,T107,T118 Yes T119,T120,T121 OUTPUT
entropy_src_hw_if_i.es_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
entropy_src_hw_if_o.es_fips Yes Yes T107,T118,T109 Yes T119,T120,T121 OUTPUT
entropy_src_hw_if_o.es_bits[383:0] Yes Yes T120,T121,T110 Yes T121,T110,T101 OUTPUT
entropy_src_hw_if_o.es_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_rng_o.rng_enable Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_rng_i.rng_b[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
entropy_src_rng_i.rng_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cs_aes_halt_o.cs_aes_halt_req Yes Yes T119,T120,T121 Yes T119,T120,T121 OUTPUT
cs_aes_halt_i.cs_aes_halt_ack Yes Yes T119,T120,T121 Yes T119,T120,T121 INPUT
entropy_src_xht_o.threshold_scope[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off / unconnected port.
entropy_src_xht_o.window_wrap_pulse Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_xht_o.health_test_window[15:0] Yes Yes *T377,*T376,*T140 Yes T377,T376,T140 OUTPUT
entropy_src_xht_o.health_test_window[17:16] No No No OUTPUT
entropy_src_xht_o.thresh_lo[13:0] Yes Yes *T133,*T131,*T132 Yes T133,T131,T132 OUTPUT
entropy_src_xht_o.thresh_lo[14] No No No OUTPUT
entropy_src_xht_o.thresh_lo[15] Yes Yes T127,T133,T131 Yes T127,T133,T131 OUTPUT
entropy_src_xht_o.thresh_hi[15:0] Yes Yes T127,T133,T132 Yes T127,T133,T132 OUTPUT
entropy_src_xht_o.active[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off / unconnected port.
entropy_src_xht_o.clear Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_xht_o.rng_bit_sel[1:0] No No No OUTPUT
entropy_src_xht_o.rng_bit_en No No No OUTPUT
entropy_src_xht_o.entropy_bit_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_xht_o.entropy_bit[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_xht_i.test_fail_lo_pulse[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off / unconnected port.
entropy_src_xht_i.test_fail_hi_pulse[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off / unconnected port.
entropy_src_xht_i.continuous_test[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off / unconnected port.
entropy_src_xht_i.test_cnt_lo[15:0] Excluded Excluded Excluded INPUT [UNR] Tied off / unconnected port.
entropy_src_xht_i.test_cnt_hi[15:0] Excluded Excluded Excluded INPUT [UNR] Tied off / unconnected port.
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[0].ping_n Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[0].ping_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[1].ping_n Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[1].ping_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
intr_es_entropy_valid_o Yes Yes T253,T317,T322 Yes T253,T317,T322 OUTPUT
intr_es_health_test_failed_o Yes Yes T253,T317,T322 Yes T253,T317,T322 OUTPUT
intr_es_observe_fifo_ready_o Yes Yes T253,T317,T322 Yes T253,T317,T322 OUTPUT
intr_es_fatal_err_o Yes Yes T253,T317,T322 Yes T253,T317,T322 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%