Unified Coverage Report :: Module :: rv_core_ibex_cfg_reg_top

Module : rv_core_ibex_cfg_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.92	100.00	99.68			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg	99.92	100.00	99.68			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.92	100.00	99.68			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.24	98.69	98.69			99.58	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.18	94.12	89.29	99.75		100.00	72.73	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_hw_err	100.00	100.00
u_alert_test_fatal_sw_err	100.00	100.00
u_alert_test_recov_hw_err	100.00	100.00
u_alert_test_recov_sw_err	100.00	100.00
u_chk	100.00	100.00					100.00
u_dbus_addr_en_0	100.00	100.00	100.00			100.00
u_dbus_addr_en_1	100.00	100.00	100.00			100.00
u_dbus_addr_matching_0	100.00	100.00	100.00			100.00
u_dbus_addr_matching_1	100.00	100.00	100.00			100.00
u_dbus_regwen_0	100.00	100.00	100.00			100.00
u_dbus_regwen_1	100.00	100.00	100.00			100.00
u_dbus_remap_addr_0	100.00	100.00	100.00			100.00
u_dbus_remap_addr_1	100.00	100.00	100.00			100.00
u_err_status_fatal_core_err	97.22	100.00	91.67			100.00
u_err_status_fatal_intg_err	100.00	100.00	100.00			100.00
u_err_status_recov_core_err	93.52	88.89	91.67			100.00
u_err_status_reg_intg_err	97.22	100.00	91.67			100.00
u_fpga_info	33.33	33.33
u_ibus_addr_en_0	100.00	100.00	100.00			100.00
u_ibus_addr_en_1	100.00	100.00	100.00			100.00
u_ibus_addr_matching_0	100.00	100.00	100.00			100.00
u_ibus_addr_matching_1	100.00	100.00	100.00			100.00
u_ibus_regwen_0	100.00	100.00	100.00			100.00
u_ibus_regwen_1	100.00	100.00	100.00			100.00
u_ibus_remap_addr_0	100.00	100.00	100.00			100.00
u_ibus_remap_addr_1	100.00	100.00	100.00			100.00
u_nmi_enable_alert_en	100.00	100.00	100.00			100.00
u_nmi_enable_wdog_en	100.00	100.00	100.00			100.00
u_nmi_state_alert	100.00	100.00	100.00			100.00
u_nmi_state_wdog	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rnd_data	100.00	100.00
u_rnd_status_rnd_data_fips	100.00	100.00
u_rnd_status_rnd_data_valid	100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	96.72	96.25	94.64			96.00	100.00
u_sw_fatal_err	100.00	100.00	100.00			100.00
u_sw_recov_err	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_core_ibex_cfg_reg_top

	Line No.	Total	Covered	Percent
TOTAL		178	178	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	607	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	729	1	1	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	793	1	1	100.00
CONT_ASSIGN	825	1	1	100.00
CONT_ASSIGN	857	1	1	100.00
ALWAYS	1174	26	26	100.00
CONT_ASSIGN	1202	1	1	100.00
ALWAYS	1206	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1237	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1241	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1252	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1268	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1294	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1298	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1302	1	1	100.00
CONT_ASSIGN	1303	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1307	1	1	100.00
CONT_ASSIGN	1308	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1312	1	1	100.00
CONT_ASSIGN	1314	1	1	100.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1318	1	1	100.00
CONT_ASSIGN	1319	1	1	100.00
ALWAYS	1323	26	26	100.00
ALWAYS	1353	36	36	100.00
CONT_ASSIGN	1475	0	0
CONT_ASSIGN	1483	1	1	100.00
CONT_ASSIGN	1484	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
100	1	1
101	1	1
103	1	1
104	1	1
130	1	1
136	1	1
137	1	1
			MISSING_ELSE
167	1	1
168	1	1
263	1	1
278	1	1
294	1	1
310	1	1
326	1	1
447	1	1
479	1	1
511	1	1
543	1	1
575	1	1
607	1	1
697	1	1
729	1	1
761	1	1
793	1	1
825	1	1
857	1	1
1174	1	1
1175	1	1
1176	1	1
1177	1	1
1178	1	1
1179	1	1
1180	1	1
1181	1	1
1182	1	1
1183	1	1
1184	1	1
1185	1	1
1186	1	1
1187	1	1
1188	1	1
1189	1	1
1190	1	1
1191	1	1
1192	1	1
1193	1	1
1194	1	1
1195	1	1
1196	1	1
1197	1	1
1198	1	1
1199	1	1
1202	1	1
1206	1	1
1235	1	1
1237	1	1
1239	1	1
1241	1	1
1243	1	1
1244	1	1
1246	1	1
1247	1	1
1249	1	1
1250	1	1
1252	1	1
1253	1	1
1255	1	1
1256	1	1
1258	1	1
1259	1	1
1261	1	1
1262	1	1
1264	1	1
1265	1	1
1267	1	1
1268	1	1
1270	1	1
1271	1	1
1273	1	1
1274	1	1
1276	1	1
1277	1	1
1279	1	1
1280	1	1
1282	1	1
1283	1	1
1285	1	1
1286	1	1
1288	1	1
1289	1	1
1291	1	1
1292	1	1
1294	1	1
1295	1	1
1297	1	1
1298	1	1
1300	1	1
1302	1	1
1303	1	1
1305	1	1
1307	1	1
1308	1	1
1310	1	1
1312	1	1
1314	1	1
1316	1	1
1317	1	1
1318	1	1
1319	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1334	1	1
1335	1	1
1336	1	1
1337	1	1
1338	1	1
1339	1	1
1340	1	1
1341	1	1
1342	1	1
1343	1	1
1344	1	1
1345	1	1
1346	1	1
1347	1	1
1348	1	1
1353	1	1
1354	1	1
1356	1	1
1357	1	1
1358	1	1
1359	1	1
1363	1	1
1367	1	1
1371	1	1
1375	1	1
1379	1	1
1383	1	1
1387	1	1
1391	1	1
1395	1	1
1399	1	1
1403	1	1
1407	1	1
1411	1	1
1415	1	1
1419	1	1
1423	1	1
1427	1	1
1431	1	1
1435	1	1
1436	1	1
1440	1	1
1441	1	1
1445	1	1
1446	1	1
1447	1	1
1448	1	1
1452	1	1
1456	1	1
1457	1	1
1461	1	1
1475		unreachable
1483	1	1
1484	1	1

---

Cond Coverage for Module : rv_core_ibex_cfg_reg_top

	Total	Covered	Percent
Conditions	311	310	99.68
Logical	311	310	99.68
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T72,T74,T80
1	1	Covered	T4,T5,T6

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T244,T245,T246
1	0	Not Covered

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T244,T245,T246
0	1	0	Covered	T79,T247,T248
1	0	0	Covered	T244,T245,T246

 LINE       130
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[128:159]}) ? 1'b0 : 1'b1)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T42

 LINE       168
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T79,T247,T248
0	1	0	Covered	T72,T74,T522
1	0	0	Covered	T72,T73,T74

 LINE       447
 EXPRESSION (ibus_addr_en_0_we & ibus_regwen_0_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T139,T375,T141
1	1	Covered	T8,T172,T302

 LINE       479
 EXPRESSION (ibus_addr_en_1_we & ibus_regwen_1_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T378,T127,T437
1	1	Covered	T8,T172,T302

 LINE       511
 EXPRESSION (ibus_addr_matching_0_we & ibus_regwen_0_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T139,T375,T378
1	1	Covered	T8,T172,T302

 LINE       543
 EXPRESSION (ibus_addr_matching_1_we & ibus_regwen_1_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T377,T140,T378
1	1	Covered	T8,T172,T302

 LINE       575
 EXPRESSION (ibus_remap_addr_0_we & ibus_regwen_0_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T139,T375,T378
1	1	Covered	T8,T172,T302

 LINE       607
 EXPRESSION (ibus_remap_addr_1_we & ibus_regwen_1_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T377,T378,T127
1	1	Covered	T8,T172,T302

 LINE       697
 EXPRESSION (dbus_addr_en_0_we & dbus_regwen_0_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T376,T140,T379
1	1	Covered	T8,T172,T302

 LINE       729
 EXPRESSION (dbus_addr_en_1_we & dbus_regwen_1_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T376,T141
1	1	Covered	T172,T302,T303

 LINE       761
 EXPRESSION (dbus_addr_matching_0_we & dbus_regwen_0_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T379,T378,T127
1	1	Covered	T8,T172,T302

 LINE       793
 EXPRESSION (dbus_addr_matching_1_we & dbus_regwen_1_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T376,T140
1	1	Covered	T172,T302,T303

 LINE       825
 EXPRESSION (dbus_remap_addr_0_we & dbus_regwen_0_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T376,T140,T379
1	1	Covered	T8,T172,T302

 LINE       857
 EXPRESSION (dbus_remap_addr_1_we & dbus_regwen_1_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T377,T376
1	1	Covered	T172,T302,T303

 LINE       1175
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_ALERT_TEST_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       1176
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_SW_RECOV_ERR_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T72,T235

 LINE       1177
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_SW_FATAL_ERR_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T647,T72,T248

 LINE       1178
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REGWEN_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1179
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REGWEN_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1180
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_EN_0_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1181
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_EN_1_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1182
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_MATCHING_0_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1183
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_MATCHING_1_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1184
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REMAP_ADDR_0_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1185
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REMAP_ADDR_1_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1186
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REGWEN_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1187
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REGWEN_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1188
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_EN_0_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1189
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_EN_1_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1190
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_MATCHING_0_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1191
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_MATCHING_1_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1192
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REMAP_ADDR_0_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1193
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REMAP_ADDR_1_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T172,T302

 LINE       1194
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_NMI_ENABLE_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       1195
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_NMI_STATE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T17,T309

 LINE       1196
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_ERR_STATUS_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T266,T277,T8

 LINE       1197
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_RND_DATA_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T53

 LINE       1198
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_RND_STATUS_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T53

 LINE       1199
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_FPGA_INFO_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T42

 LINE       1202
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       1202
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       1206
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T72,T74,T522

 LINE       1206
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b0011 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T4,T5,T6
25 (addr_hit[24] & ((|(4'...	Covered	T248,T515,T489
24 (addr_hit[23] & ((|(4'...	Covered	T72,T248,T515
23 (addr_hit[22] & ((|(4'...	Covered	T72,T79,T235
22 (addr_hit[21] & ((|(4'...	Covered	T248,T377,T515
21 (addr_hit[20] & ((|(4'...	Covered	T72,T247,T248
20 (addr_hit[19] & ((|(4'...	Covered	T79,T247,T522
19 (addr_hit[18] & ((|(4'...	Covered	T72,T79,T247
18 (addr_hit[17] & ((|(4'...	Covered	T72,T80,T79
17 (addr_hit[16] & ((|(4'...	Covered	T72,T79,T247
16 (addr_hit[15] & ((|(4'...	Covered	T72,T74,T79
15 (addr_hit[14] & ((|(4'...	Covered	T79,T248,T377
14 (addr_hit[13] & ((|(4'...	Covered	T72,T79,T522
13 (addr_hit[12] & ((|(4'...	Covered	T72,T80,T79
12 (addr_hit[11] & ((|(4'...	Covered	T530,T247,T248
11 (addr_hit[10] & ((|(4'...	Covered	T72,T79,T235
10 (addr_hit[9] & ((|(4'b...	Covered	T72,T79,T247
9 (addr_hit[8] & ((|(4'b...	Covered	T72,T80,T79
8 (addr_hit[7] & ((|(4'b...	Covered	T72,T248,T489
7 (addr_hit[6] & ((|(4'b...	Covered	T80,T79,T247
6 (addr_hit[5] & ((|(4'b...	Covered	T79,T248,T377
5 (addr_hit[4] & ((|(4'b...	Covered	T72,T235,T248
4 (addr_hit[3] & ((|(4'b...	Covered	T72,T79,T235
3 (addr_hit[2] & ((|(4'b...	Covered	T72,T248,T489
2 (addr_hit[1] & ((|(4'b...	Covered	T72,T235,T248
1 (addr_hit[0] & ((|(4'b...	Covered	T4,T5,T6

 LINE       1206
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T72,T73,T74
1	0	Covered	T4,T147,T152
1	1	Covered	T4,T5,T6

 LINE       1206
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T72,T248
1	1	Covered	T72,T235,T248

 LINE       1206
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T647,T72,T248
1	1	Covered	T72,T248,T489

 LINE       1206
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T72,T79,T235

 LINE       1206
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T72,T235,T248

 LINE       1206
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T79,T248,T377

 LINE       1206
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T80,T79,T247

 LINE       1206
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T72,T248,T489

 LINE       1206
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T72,T80,T79

 LINE       1206
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T72,T79,T247

 LINE       1206
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T72,T79,T235

 LINE       1206
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T530,T247,T248

 LINE       1206
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T72,T80,T79

 LINE       1206
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T72,T79,T522

 LINE       1206
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T79,T248,T377

 LINE       1206
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T72,T74,T79

 LINE       1206
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T72,T79,T247

 LINE       1206
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T72,T80,T79

 LINE       1206
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T172,T302
1	1	Covered	T72,T79,T247

 LINE       1206
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T79,T247,T522

 LINE       1206
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T17,T309
1	1	Covered	T72,T247,T248

 LINE       1206
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T266,T277,T8
1	1	Covered	T248,T377,T515

 LINE       1206
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T53
1	1	Covered	T72,T79,T235

 LINE       1206
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T53
1	1	Covered	T72,T248,T515

 LINE       1206
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T42
1	1	Covered	T248,T515,T489

 LINE       1235
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T72,T489,T447
1	1	1	Covered	T4,T147,T152

 LINE       1244
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T72,T235,T521
1	1	0	Covered	T491,T447,T452
1	1	1	Covered	T8,T72,T377

 LINE       1247
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T72,T489,T523
1	1	0	Covered	T447,T533,T543
1	1	1	Covered	T647,T72,T489

 LINE       1250
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T172,T302
1	1	0	Covered	T491,T535,T452
1	1	1	Covered	T8,T72,T377

 LINE       1253
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T172,T302
1	1	0	Covered	T447,T537,T441
1	1	1	Covered	T8,T74,T377

 LINE       1256
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T377,T538
1	1	0	Covered	T447,T517,T537
1	1	1	Covered	T8,T172,T302

 LINE       1259
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T80,T377
1	1	0	Covered	T447,T537,T532
1	1	1	Covered	T8,T172,T302

 LINE       1262
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T72,T377
1	1	0	Covered	T72,T489,T451
1	1	1	Covered	T8,T172,T302

 LINE       1265
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T80,T530
1	1	0	Covered	T72,T447,T452
1	1	1	Covered	T8,T172,T302

 LINE       1268
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T72,T377
1	1	0	Covered	T491,T447,T452
1	1	1	Covered	T8,T172,T302

 LINE       1271
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T72,T235
1	1	0	Covered	T72,T489,T451
1	1	1	Covered	T8,T172,T302

 LINE       1274
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T172,T302
1	1	0	Covered	T447,T452,T517
1	1	1	Covered	T8,T72,T74

 LINE       1277
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T172,T302
1	1	0	Covered	T489,T452,T517
1	1	1	Covered	T8,T377,T489

 LINE       1280
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T72,T522
1	1	0	Covered	T72,T447,T452
1	1	1	Covered	T8,T172,T302

 LINE       1283
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T377,T489
1	1	0	Covered	T489,T447,T452
1	1	1	Covered	T8,T172,T302

 LINE       1286
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T72,T74
1	1	0	Covered	T74,T522,T451
1	1	1	Covered	T8,T172,T302

 LINE       1289
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T72,T377
1	1	0	Covered	T447,T452,T578
1	1	1	Covered	T8,T172,T302

 LINE       1292
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T72,T80
1	1	0	Covered	T452,T537,T543
1	1	1	Covered	T8,T172,T302

 LINE       1295
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T72,T377
1	1	0	Covered	T491,T447,T452
1	1	1	Covered	T8,T172,T302

 LINE       1298
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T147,T152
1	0	1	Covered	T5,T17,T309
1	1	0	Covered	T452,T537,T441
1	1	1	Covered	T4,T5,T6

 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T5,T17,T309
1	1	0	Covered	T489,T451,T447
1	1	1	Covered	T178,T8,T508

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T266,T277,T8
1	1	0	Covered	T447,T452,T537
1	1	1	Covered	T8,T74,T377

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T235,T377
1	1	0	Covered	T648
1	1	1	Covered	T5,T6,T53

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T8,T377,T527
1	1	0	Covered	T649,T650,T651
1	1	1	Covered	T5,T6,T53

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T53
1	0	1	Covered	T8,T377,T489
1	1	0	Covered	T652
1	1	1	Covered	T4,T5,T42

---

Branch Coverage for Module : rv_core_ibex_cfg_reg_top

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	1202	2	2	100.00
IF	73	3	3	100.00
TERNARY	130	2	2	100.00
IF	136	2	2	100.00
CASE	1354	26	26	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1202	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T244,T245,T246
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	130	((tl_i.a_address[(AW - 1):0] inside {[128:159]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	136	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T79,T247,T248
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1354	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T4,T5,T6
addr_hit[1]	Covered	T8,T72,T235
addr_hit[2]	Covered	T647,T72,T248
addr_hit[3]	Covered	T8,T172,T302
addr_hit[4]	Covered	T8,T172,T302
addr_hit[5]	Covered	T8,T172,T302
addr_hit[6]	Covered	T8,T172,T302
addr_hit[7]	Covered	T8,T172,T302
addr_hit[8]	Covered	T8,T172,T302
addr_hit[9]	Covered	T8,T172,T302
addr_hit[10]	Covered	T8,T172,T302
addr_hit[11]	Covered	T8,T172,T302
addr_hit[12]	Covered	T8,T172,T302
addr_hit[13]	Covered	T8,T172,T302
addr_hit[14]	Covered	T8,T172,T302
addr_hit[15]	Covered	T8,T172,T302
addr_hit[16]	Covered	T8,T172,T302
addr_hit[17]	Covered	T8,T172,T302
addr_hit[18]	Covered	T8,T172,T302
addr_hit[19]	Covered	T4,T5,T6
addr_hit[20]	Covered	T5,T17,T309
addr_hit[21]	Covered	T266,T277,T8
addr_hit[22]	Covered	T5,T6,T53
addr_hit[23]	Covered	T5,T6,T53
addr_hit[24]	Covered	T4,T5,T42
default	Covered	T4,T5,T42

---

Assert Coverage for Module : rv_core_ibex_cfg_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	558412117	34796	0	0
reAfterRv	558412117	34796	0	0
rePulse	558412117	29534	0	0
wePulse	558412117	5262	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	34796	0	0
T4	251635	4	0	0
T5	289141	56	0	0
T6	194596	29	0	0
T17	267143	56	0	0
T18	0	3	0	0
T19	853528	0	0	0
T20	302519	3	0	0
T42	102547	1	0	0
T53	917879	29	0	0
T55	115818	0	0	0
T56	0	4	0	0
T68	640996	0	0	0
T111	0	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	34796	0	0
T4	251635	4	0	0
T5	289141	56	0	0
T6	194596	29	0	0
T17	267143	56	0	0
T18	0	3	0	0
T19	853528	0	0	0
T20	302519	3	0	0
T42	102547	1	0	0
T53	917879	29	0	0
T55	115818	0	0	0
T56	0	4	0	0
T68	640996	0	0	0
T111	0	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	29534	0	0
T4	251635	2	0	0
T5	289141	54	0	0
T6	194596	22	0	0
T17	267143	54	0	0
T18	0	3	0	0
T19	853528	0	0	0
T20	302519	3	0	0
T42	102547	1	0	0
T53	917879	28	0	0
T55	115818	0	0	0
T56	0	4	0	0
T68	640996	0	0	0
T111	0	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	558412117	5262	0	0
T4	251635	2	0	0
T5	289141	2	0	0
T6	194596	7	0	0
T17	267143	2	0	0
T19	853528	0	0	0
T20	302519	0	0	0
T42	102547	0	0	0
T53	917879	1	0	0
T54	0	1	0	0
T55	115818	0	0	0
T68	640996	0	0	0
T147	0	1	0	0
T309	0	2	0	0
T314	0	1	0	0
T315	0	2	0	0