Toggle Coverage for Module :
rv_timer
| Total | Covered | Percent |
Totals |
30 |
30 |
100.00 |
Total Bits |
292 |
292 |
100.00 |
Total Bits 0->1 |
146 |
146 |
100.00 |
Total Bits 1->0 |
146 |
146 |
100.00 |
| | | |
Ports |
30 |
30 |
100.00 |
Port Bits |
292 |
292 |
100.00 |
Port Bits 0->1 |
146 |
146 |
100.00 |
Port Bits 1->0 |
146 |
146 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T337,T250,T178 |
Yes |
T337,T250,T178 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T337,T250,T178 |
Yes |
T337,T250,T178 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[8:0] |
Yes |
Yes |
*T72,*T73,*T74 |
Yes |
T72,T73,T74 |
INPUT |
tl_i.a_address[19:9] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[20] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T55,*T75,*T76 |
Yes |
T55,T75,T76 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T72,T73,T74 |
Yes |
T72,T73,T74 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T55,T77,T78 |
Yes |
T55,T77,T78 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T337,T250,T178 |
Yes |
T337,T250,T178 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T337,T250,T178 |
Yes |
T337,T250,T178 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T72,T73,T74 |
Yes |
T72,T73,T74 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T337,T250,T78 |
Yes |
T337,T250,T78 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T337,T250,T178 |
Yes |
T337,T250,T178 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T337,T250,T178 |
Yes |
T337,T250,T178 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T72,T74,T80 |
Yes |
T72,T73,T74 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T78,*T72,*T80 |
Yes |
T78,T72,T73 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T72,T73,T74 |
Yes |
T72,T73,T74 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T337,*T250,*T178 |
Yes |
T337,T250,T178 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T337,T250,T178 |
Yes |
T337,T250,T178 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T81,T82,T682 |
Yes |
T81,T82,T682 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T81,T82,T682 |
Yes |
T81,T82,T83 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T682 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T81,T82,T682 |
Yes |
T81,T82,T682 |
OUTPUT |
intr_timer_expired_hart0_timer0_o |
Yes |
Yes |
T250,T148,T251 |
Yes |
T250,T148,T251 |
OUTPUT |
*Tests covering at least one bit in the range