Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T172,T302
0	1	Covered	T172,T302,T303
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T172,T302,T303
1	Covered	T8,T172,T302

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T172,T302,T303
1	Covered	T8,T172,T302

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T172,T302,T303
1	1	Covered	T172,T302,T303

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T172,T302
1	0	Covered	T172,T302,T303
1	1	Covered	T172,T302,T303

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T172,T302,T303

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T172,T302
0	Covered	T172,T302,T303

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T172,T302
0	Covered	T172,T302,T303

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	956814576	939177424	0	0
CheckNGreaterZero_A	1988	1988	0	0
GntImpliesReady_A	956814576	8368	0	0
GntImpliesValid_A	956814576	8368	0	0
GrantKnown_A	956814576	939177424	0	0
IdxKnown_A	956814576	939177424	0	0
IndexIsCorrect_A	956814576	8368	0	0
NoReadyValidNoGrant_A	956814576	0	0	0
Priority_A	956814576	8368	0	0
ReadyAndValidImplyGrant_A	956814576	8368	0	0
ReqAndReadyImplyGrant_A	956814576	8368	0	0
ReqImpliesValid_A	956814576	8368	0	0
ValidKnown_A	956814576	939177424	0	0
gen_data_port_assertion.DataFlow_A	956814576	8368	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	939177424	0	0
T4	503270	503036	0	0
T5	578282	578056	0	0
T6	389192	389100	0	0
T17	534286	534052	0	0
T19	1707056	1705852	0	0
T20	605038	604600	0	0
T42	205094	204984	0	0
T53	1835758	1835648	0	0
T55	231636	0	0	0
T56	0	760272	0	0
T68	1281992	1281876	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1988	1988	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T17	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T42	2	2	0	0
T53	2	2	0	0
T55	2	2	0	0
T68	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	8368	0	0
T172	227478	2782	0	0
T260	452208	0	0	0
T278	569512	0	0	0
T302	0	2794	0	0
T303	0	2792	0	0
T390	907722	0	0	0
T391	576390	0	0	0
T392	197748	0	0	0
T393	286438	0	0	0
T394	405112	0	0	0
T395	270214	0	0	0
T396	248524	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	8368	0	0
T172	227478	2782	0	0
T260	452208	0	0	0
T278	569512	0	0	0
T302	0	2794	0	0
T303	0	2792	0	0
T390	907722	0	0	0
T391	576390	0	0	0
T392	197748	0	0	0
T393	286438	0	0	0
T394	405112	0	0	0
T395	270214	0	0	0
T396	248524	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	939177424	0	0
T4	503270	503036	0	0
T5	578282	578056	0	0
T6	389192	389100	0	0
T17	534286	534052	0	0
T19	1707056	1705852	0	0
T20	605038	604600	0	0
T42	205094	204984	0	0
T53	1835758	1835648	0	0
T55	231636	0	0	0
T56	0	760272	0	0
T68	1281992	1281876	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	939177424	0	0
T4	503270	503036	0	0
T5	578282	578056	0	0
T6	389192	389100	0	0
T17	534286	534052	0	0
T19	1707056	1705852	0	0
T20	605038	604600	0	0
T42	205094	204984	0	0
T53	1835758	1835648	0	0
T55	231636	0	0	0
T56	0	760272	0	0
T68	1281992	1281876	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	8368	0	0
T172	227478	2782	0	0
T260	452208	0	0	0
T278	569512	0	0	0
T302	0	2794	0	0
T303	0	2792	0	0
T390	907722	0	0	0
T391	576390	0	0	0
T392	197748	0	0	0
T393	286438	0	0	0
T394	405112	0	0	0
T395	270214	0	0	0
T396	248524	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	8368	0	0
T172	227478	2782	0	0
T260	452208	0	0	0
T278	569512	0	0	0
T302	0	2794	0	0
T303	0	2792	0	0
T390	907722	0	0	0
T391	576390	0	0	0
T392	197748	0	0	0
T393	286438	0	0	0
T394	405112	0	0	0
T395	270214	0	0	0
T396	248524	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	8368	0	0
T172	227478	2782	0	0
T260	452208	0	0	0
T278	569512	0	0	0
T302	0	2794	0	0
T303	0	2792	0	0
T390	907722	0	0	0
T391	576390	0	0	0
T392	197748	0	0	0
T393	286438	0	0	0
T394	405112	0	0	0
T395	270214	0	0	0
T396	248524	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	8368	0	0
T172	227478	2782	0	0
T260	452208	0	0	0
T278	569512	0	0	0
T302	0	2794	0	0
T303	0	2792	0	0
T390	907722	0	0	0
T391	576390	0	0	0
T392	197748	0	0	0
T393	286438	0	0	0
T394	405112	0	0	0
T395	270214	0	0	0
T396	248524	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	8368	0	0
T172	227478	2782	0	0
T260	452208	0	0	0
T278	569512	0	0	0
T302	0	2794	0	0
T303	0	2792	0	0
T390	907722	0	0	0
T391	576390	0	0	0
T392	197748	0	0	0
T393	286438	0	0	0
T394	405112	0	0	0
T395	270214	0	0	0
T396	248524	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	939177424	0	0
T4	503270	503036	0	0
T5	578282	578056	0	0
T6	389192	389100	0	0
T17	534286	534052	0	0
T19	1707056	1705852	0	0
T20	605038	604600	0	0
T42	205094	204984	0	0
T53	1835758	1835648	0	0
T55	231636	0	0	0
T56	0	760272	0	0
T68	1281992	1281876	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956814576	8368	0	0
T172	227478	2782	0	0
T260	452208	0	0	0
T278	569512	0	0	0
T302	0	2794	0	0
T303	0	2792	0	0
T390	907722	0	0	0
T391	576390	0	0	0
T392	197748	0	0	0
T393	286438	0	0	0
T394	405112	0	0	0
T395	270214	0	0	0
T396	248524	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T172,T302
0	1	Covered	T172,T302,T303
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T172,T302,T303
1	Covered	T8,T172,T302

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T172,T302,T303
1	Covered	T8,T172,T302

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T172,T302,T303
1	1	Covered	T172,T302,T303

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T172,T302
1	0	Covered	T172,T302,T303
1	1	Covered	T172,T302,T303

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T172,T302,T303

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T172,T302
0	Covered	T172,T302,T303

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T172,T302
0	Covered	T172,T302,T303

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	478407288	469588712	0	0
CheckNGreaterZero_A	994	994	0	0
GntImpliesReady_A	478407288	5178	0	0
GntImpliesValid_A	478407288	5178	0	0
GrantKnown_A	478407288	469588712	0	0
IdxKnown_A	478407288	469588712	0	0
IndexIsCorrect_A	478407288	5178	0	0
NoReadyValidNoGrant_A	478407288	0	0	0
Priority_A	478407288	5178	0	0
ReadyAndValidImplyGrant_A	478407288	5178	0	0
ReqAndReadyImplyGrant_A	478407288	5178	0	0
ReqImpliesValid_A	478407288	5178	0	0
ValidKnown_A	478407288	469588712	0	0
gen_data_port_assertion.DataFlow_A	478407288	5178	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	469588712	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	0	0	0
T56	0	380136	0	0
T68	640996	640938	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T68	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	5178	0	0
T172	113739	1718	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1730	0	0
T303	0	1730	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	5178	0	0
T172	113739	1718	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1730	0	0
T303	0	1730	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	469588712	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	0	0	0
T56	0	380136	0	0
T68	640996	640938	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	469588712	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	0	0	0
T56	0	380136	0	0
T68	640996	640938	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	5178	0	0
T172	113739	1718	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1730	0	0
T303	0	1730	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	5178	0	0
T172	113739	1718	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1730	0	0
T303	0	1730	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	5178	0	0
T172	113739	1718	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1730	0	0
T303	0	1730	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	5178	0	0
T172	113739	1718	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1730	0	0
T303	0	1730	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	5178	0	0
T172	113739	1718	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1730	0	0
T303	0	1730	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	469588712	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	0	0	0
T56	0	380136	0	0
T68	640996	640938	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	5178	0	0
T172	113739	1718	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1730	0	0
T303	0	1730	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T172,T302
0	1	Covered	T172,T302,T303
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T172,T302,T303
1	Covered	T8,T172,T302

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T172,T302,T303
1	Covered	T8,T172,T302

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T172,T302,T303
1	1	Covered	T172,T302,T303

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T172,T302
1	0	Covered	T172,T302,T303
1	1	Covered	T172,T302,T303

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T172,T302,T303

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T172,T302
0	Covered	T172,T302,T303

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T172,T302
0	Covered	T172,T302,T303

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	478407288	469588712	0	0
CheckNGreaterZero_A	994	994	0	0
GntImpliesReady_A	478407288	3190	0	0
GntImpliesValid_A	478407288	3190	0	0
GrantKnown_A	478407288	469588712	0	0
IdxKnown_A	478407288	469588712	0	0
IndexIsCorrect_A	478407288	3190	0	0
NoReadyValidNoGrant_A	478407288	0	0	0
Priority_A	478407288	3190	0	0
ReadyAndValidImplyGrant_A	478407288	3190	0	0
ReqAndReadyImplyGrant_A	478407288	3190	0	0
ReqImpliesValid_A	478407288	3190	0	0
ValidKnown_A	478407288	469588712	0	0
gen_data_port_assertion.DataFlow_A	478407288	3190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	469588712	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	0	0	0
T56	0	380136	0	0
T68	640996	640938	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T68	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	3190	0	0
T172	113739	1064	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1064	0	0
T303	0	1062	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	3190	0	0
T172	113739	1064	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1064	0	0
T303	0	1062	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	469588712	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	0	0	0
T56	0	380136	0	0
T68	640996	640938	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	469588712	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	0	0	0
T56	0	380136	0	0
T68	640996	640938	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	3190	0	0
T172	113739	1064	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1064	0	0
T303	0	1062	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	3190	0	0
T172	113739	1064	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1064	0	0
T303	0	1062	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	3190	0	0
T172	113739	1064	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1064	0	0
T303	0	1062	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	3190	0	0
T172	113739	1064	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1064	0	0
T303	0	1062	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	3190	0	0
T172	113739	1064	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1064	0	0
T303	0	1062	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	469588712	0	0
T4	251635	251518	0	0
T5	289141	289028	0	0
T6	194596	194550	0	0
T17	267143	267026	0	0
T19	853528	852926	0	0
T20	302519	302300	0	0
T42	102547	102492	0	0
T53	917879	917824	0	0
T55	115818	0	0	0
T56	0	380136	0	0
T68	640996	640938	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478407288	3190	0	0
T172	113739	1064	0	0
T260	226104	0	0	0
T278	284756	0	0	0
T302	0	1064	0	0
T303	0	1062	0	0
T390	453861	0	0	0
T391	288195	0	0	0
T392	98874	0	0	0
T393	143219	0	0	0
T394	202556	0	0	0
T395	135107	0	0	0
T396	124262	0	0	0