SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.83 | 99.34 | 100.00 | 100.00 | 100.00 | u_pinmux_strap_sampling |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 994 | 994 | 0 | 0 |
OutputsKnown_A | 119912679 | 119252284 | 0 | 0 |
gen_no_flops.OutputDelay_A | 119912679 | 119252284 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 994 | 994 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T42 | 1 | 1 | 0 | 0 |
T53 | 1 | 1 | 0 | 0 |
T55 | 1 | 1 | 0 | 0 |
T68 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119912679 | 119252284 | 0 | 0 |
T4 | 61703 | 61133 | 0 | 0 |
T5 | 70451 | 70134 | 0 | 0 |
T6 | 472229 | 469617 | 0 | 0 |
T17 | 65375 | 64854 | 0 | 0 |
T19 | 213590 | 208895 | 0 | 0 |
T20 | 76892 | 75728 | 0 | 0 |
T42 | 25608 | 24980 | 0 | 0 |
T53 | 221116 | 220675 | 0 | 0 |
T55 | 278943 | 278314 | 0 | 0 |
T68 | 154756 | 154216 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119912679 | 119252284 | 0 | 0 |
T4 | 61703 | 61133 | 0 | 0 |
T5 | 70451 | 70134 | 0 | 0 |
T6 | 472229 | 469617 | 0 | 0 |
T17 | 65375 | 64854 | 0 | 0 |
T19 | 213590 | 208895 | 0 | 0 |
T20 | 76892 | 75728 | 0 | 0 |
T42 | 25608 | 24980 | 0 | 0 |
T53 | 221116 | 220675 | 0 | 0 |
T55 | 278943 | 278314 | 0 | 0 |
T68 | 154756 | 154216 | 0 | 0 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 994 | 994 | 0 | 0 |
OutputsKnown_A | 119912679 | 119252284 | 0 | 0 |
gen_no_flops.OutputDelay_A | 119912679 | 119252284 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 994 | 994 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T42 | 1 | 1 | 0 | 0 |
T53 | 1 | 1 | 0 | 0 |
T55 | 1 | 1 | 0 | 0 |
T68 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119912679 | 119252284 | 0 | 0 |
T4 | 61703 | 61133 | 0 | 0 |
T5 | 70451 | 70134 | 0 | 0 |
T6 | 472229 | 469617 | 0 | 0 |
T17 | 65375 | 64854 | 0 | 0 |
T19 | 213590 | 208895 | 0 | 0 |
T20 | 76892 | 75728 | 0 | 0 |
T42 | 25608 | 24980 | 0 | 0 |
T53 | 221116 | 220675 | 0 | 0 |
T55 | 278943 | 278314 | 0 | 0 |
T68 | 154756 | 154216 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119912679 | 119252284 | 0 | 0 |
T4 | 61703 | 61133 | 0 | 0 |
T5 | 70451 | 70134 | 0 | 0 |
T6 | 472229 | 469617 | 0 | 0 |
T17 | 65375 | 64854 | 0 | 0 |
T19 | 213590 | 208895 | 0 | 0 |
T20 | 76892 | 75728 | 0 | 0 |
T42 | 25608 | 24980 | 0 | 0 |
T53 | 221116 | 220675 | 0 | 0 |
T55 | 278943 | 278314 | 0 | 0 |
T68 | 154756 | 154216 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |