Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3741574	1			T73	2395		T74	88		T75	110
values[2]	757572	1			T74	22		T75	37		T117	681
values[3]	111878	1			T74	26		T75	30		T117	145
values[4]	59286	1			T74	3		T117	55		T226	13
values[5]	39907	1			T117	25		T226	3		T420	108
values[6]	29848	1			T117	15		T420	95		T527	7
values[7]	24602	1			T117	2		T420	84		T527	7
values[8]	21218	1			T117	1		T420	47		T527	8
values[9]	18284	1			T420	31		T527	7		T519	84
values[10]	16383	1			T420	20		T527	7		T519	49
values[11]	14795	1			T420	25		T527	7		T519	26
values[12]	13693	1			T420	18		T527	8		T519	24
values[13]	12998	1			T420	8		T527	7		T519	19
values[14]	12324	1			T420	10		T527	7		T519	17
values[15]	11943	1			T420	12		T527	7		T519	4
values[16]	11584	1			T420	10		T527	7		T528	9
values[17]	11073	1			T420	10		T527	7		T528	9
values[18]	10652	1			T420	8		T527	7		T528	9
values[19]	10576	1			T420	9		T527	7		T528	9
values[20]	10265	1			T420	10		T527	7		T528	9
values[21]	9905	1			T420	13		T527	8		T528	10
values[22]	9436	1			T420	3		T527	7		T528	9
values[23]	9094	1			T420	7		T527	7		T528	9
values[24]	8578	1			T420	7		T527	8		T528	9
values[25]	8282	1			T420	18		T527	7		T528	10
values[26]	7764	1			T420	11		T527	7		T528	9
values[27]	7474	1			T420	8		T527	7		T528	9
values[28]	7133	1			T420	3		T527	7		T528	9
values[29]	6595	1			T420	3		T527	8		T528	9
values[30]	6330	1			T420	2		T527	7		T528	9
values[31]	6003	1			T420	1		T527	7		T528	9
values[32]	5610	1			T420	4		T527	7		T528	9
values[33]	5314	1			T420	1		T527	7		T528	9
values[34]	4970	1			T420	2		T527	8		T528	10
values[35]	4640	1			T420	2		T527	7		T528	10
values[36]	4344	1			T420	4		T527	7		T528	10
values[37]	4153	1			T420	2		T527	7		T528	9
values[38]	3956	1			T420	1		T527	7		T528	9
values[39]	3920	1			T420	2		T527	7		T528	9
values[40]	3775	1			T420	2		T527	8		T528	9
values[41]	3699	1			T420	2		T527	7		T528	10
values[42]	3611	1			T420	1		T527	7		T528	9
values[43]	3459	1			T420	1		T527	7		T528	9
values[44]	3399	1			T420	1		T527	7		T528	9
values[45]	3305	1			T420	2		T527	7		T528	9
values[46]	3286	1			T420	2		T527	7		T528	9
values[47]	3269	1			T420	1		T527	8		T528	9
values[48]	3142	1			T420	3		T527	7		T528	10
values[49]	3087	1			T420	4		T527	7		T528	9
values[50]	2901	1			T420	2		T527	7		T528	9
values[51]	2905	1			T420	1		T527	7		T528	9
values[52]	2849	1			T420	1		T527	7		T528	9
values[53]	2782	1			T420	1		T527	7		T528	9
values[54]	2699	1			T420	1		T527	7		T528	10
values[55]	2727	1			T420	2		T527	7		T528	9
values[56]	2721	1			T420	2		T527	7		T528	9
values[57]	2695	1			T420	1		T527	7		T528	9
values[58]	2622	1			T420	1		T527	7		T528	9
values[59]	2649	1			T420	1		T527	7		T528	9
values[60]	2723	1			T420	6		T527	7		T528	9
values[61]	2951	1			T420	4		T527	7		T528	9
values[62]	4411	1			T420	3		T527	7		T528	9
values[63]	12341	1			T420	25		T527	7		T528	10
values[64]	229134	1			T420	47		T527	1375		T528	1639

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4806022	1			T73	2308		T74	128		T75	67
values[2]	817385	1			T74	31		T75	28		T117	631
values[3]	84979	1			T74	11		T75	7		T117	107
values[4]	14799	1			T74	1		T117	13		T368	1
values[5]	5557	1			T74	1		T117	2		T226	7
values[6]	3491	1			T74	1		T226	2		T420	8
values[7]	2732	1			T74	1		T420	1		T527	2
values[8]	2230	1			T74	1		T420	2		T527	1
values[9]	2070	1			T420	5		T527	1		T524	24
values[10]	1979	1			T420	6		T527	1		T524	20
values[11]	1688	1			T420	10		T527	1		T524	25
values[12]	1554	1			T420	6		T527	1		T524	24
values[13]	1431	1			T420	5		T527	1		T524	15
values[14]	1350	1			T420	4		T527	1		T524	13
values[15]	1317	1			T420	7		T527	1		T524	7
values[16]	1146	1			T420	6		T527	1		T524	8
values[17]	1000	1			T420	8		T527	1		T524	8
values[18]	972	1			T420	5		T527	1		T524	7
values[19]	1018	1			T420	9		T527	1		T524	7
values[20]	1008	1			T420	11		T527	1		T524	4
values[21]	934	1			T420	8		T527	1		T524	8
values[22]	928	1			T420	4		T527	1		T524	8
values[23]	894	1			T420	8		T527	1		T524	4
values[24]	821	1			T420	4		T527	1		T524	4
values[25]	812	1			T420	1		T527	1		T524	2
values[26]	765	1			T420	1		T527	1		T524	2
values[27]	789	1			T420	2		T527	1		T524	10
values[28]	746	1			T420	2		T527	1		T524	6
values[29]	750	1			T420	3		T527	1		T524	4
values[30]	775	1			T420	4		T527	1		T524	6
values[31]	663	1			T420	2		T527	2		T524	3
values[32]	623	1			T527	1		T524	6		T400	2
values[33]	583	1			T527	1		T524	5		T400	2
values[34]	611	1			T527	1		T524	18		T400	2
values[35]	607	1			T527	1		T524	10		T400	2
values[36]	555	1			T527	1		T524	6		T400	2
values[37]	524	1			T527	1		T524	2		T400	2
values[38]	554	1			T527	1		T524	4		T400	3
values[39]	527	1			T527	1		T524	5		T400	2
values[40]	542	1			T527	1		T524	7		T400	2
values[41]	513	1			T527	1		T524	5		T400	1
values[42]	463	1			T527	1		T524	6		T400	1
values[43]	454	1			T527	1		T524	5		T400	2
values[44]	426	1			T527	1		T524	3		T400	2
values[45]	446	1			T527	1		T524	3		T400	2
values[46]	439	1			T527	1		T524	4		T400	2
values[47]	436	1			T527	1		T524	2		T400	2
values[48]	407	1			T527	1		T524	2		T400	2
values[49]	446	1			T527	1		T524	5		T400	2
values[50]	433	1			T527	1		T524	7		T400	2
values[51]	465	1			T527	1		T524	6		T400	2
values[52]	442	1			T527	1		T524	3		T400	2
values[53]	397	1			T527	1		T524	11		T400	2
values[54]	407	1			T527	1		T524	7		T400	2
values[55]	386	1			T527	1		T524	2		T400	2
values[56]	379	1			T527	1		T524	2		T400	3
values[57]	426	1			T527	1		T524	7		T400	2
values[58]	444	1			T527	1		T524	7		T400	2
values[59]	426	1			T527	1		T524	7		T400	2
values[60]	443	1			T527	1		T524	11		T400	2
values[61]	456	1			T527	1		T524	22		T400	2
values[62]	765	1			T527	1		T524	37		T400	2
values[63]	2692	1			T527	1		T524	40		T400	2
values[64]	26599	1			T527	151		T524	39		T400	12

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	553968	1			T73	2294		T74	1		T75	1
values[2]	2678089	1			T74	1		T75	1		T117	1208
values[3]	1201820	1			T74	66		T75	72		T117	1244
values[4]	155030	1			T74	35		T75	25		T117	143
values[5]	79976	1			T74	5		T75	2		T117	104
values[6]	52880	1			T117	56		T226	1		T420	43
values[7]	39013	1			T117	32		T420	34		T527	7
values[8]	30711	1			T117	10		T420	37		T527	7
values[9]	25560	1			T117	3		T420	39		T527	7
values[10]	22194	1			T117	1		T420	20		T527	7
values[11]	20219	1			T117	2		T420	15		T527	7
values[12]	18557	1			T117	1		T420	10		T527	7
values[13]	17514	1			T420	18		T527	7		T519	66
values[14]	16282	1			T420	21		T527	7		T519	55
values[15]	15515	1			T420	12		T527	7		T519	25
values[16]	14588	1			T420	8		T527	7		T519	12
values[17]	13750	1			T420	6		T527	7		T519	14
values[18]	13220	1			T420	8		T527	7		T519	5
values[19]	12669	1			T420	9		T527	7		T519	1
values[20]	12008	1			T420	5		T527	7		T528	9
values[21]	11353	1			T420	4		T527	7		T528	9
values[22]	11228	1			T420	3		T527	7		T528	10
values[23]	10756	1			T420	3		T527	7		T528	9
values[24]	10234	1			T420	2		T527	7		T528	9
values[25]	9870	1			T420	9		T527	7		T528	9
values[26]	9184	1			T420	4		T527	7		T528	9
values[27]	8668	1			T420	12		T527	7		T528	9
values[28]	8252	1			T420	11		T527	7		T528	9
values[29]	7852	1			T420	5		T527	7		T528	9
values[30]	7196	1			T420	5		T527	7		T528	9
values[31]	6564	1			T420	3		T527	7		T528	9
values[32]	6237	1			T420	5		T527	7		T528	9
values[33]	5823	1			T420	2		T527	7		T528	9
values[34]	5479	1			T420	2		T527	7		T528	9
values[35]	5029	1			T420	3		T527	7		T528	9
values[36]	4871	1			T420	8		T527	7		T528	9
values[37]	4599	1			T420	7		T527	7		T528	9
values[38]	4452	1			T420	2		T527	8		T528	9
values[39]	4084	1			T420	3		T527	7		T528	9
values[40]	4009	1			T420	3		T527	7		T528	10
values[41]	3889	1			T420	6		T527	7		T528	9
values[42]	3794	1			T420	5		T527	7		T528	9
values[43]	3732	1			T420	4		T527	7		T528	9
values[44]	3654	1			T420	4		T527	7		T528	9
values[45]	3571	1			T420	9		T527	7		T528	10
values[46]	3539	1			T420	8		T527	7		T528	9
values[47]	3383	1			T420	5		T527	7		T528	9
values[48]	3327	1			T420	4		T527	7		T528	9
values[49]	3379	1			T420	9		T527	7		T528	9
values[50]	3422	1			T420	2		T527	7		T528	10
values[51]	3207	1			T420	4		T527	7		T528	9
values[52]	3073	1			T420	4		T527	7		T528	9
values[53]	3049	1			T420	7		T527	7		T528	9
values[54]	3075	1			T420	6		T527	7		T528	9
values[55]	2901	1			T420	2		T527	7		T528	9
values[56]	2968	1			T420	6		T527	7		T528	10
values[57]	2898	1			T420	12		T527	7		T528	9
values[58]	2807	1			T420	4		T527	7		T528	9
values[59]	2759	1			T420	7		T527	7		T528	9
values[60]	2797	1			T420	6		T527	7		T528	9
values[61]	3021	1			T420	8		T527	7		T528	9
values[62]	4189	1			T420	18		T527	7		T528	9
values[63]	10754	1			T420	32		T527	8		T528	9
values[64]	219528	1			T420	118		T527	1159		T528	1786