Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2364073	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33732393

1

T4

5007

T6

11359

T15

104798

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	24529366	1			T4	1900		T6	4810		T15	78154
values[0x0]	9717837	1			T4	3107		T6	6549		T15	26644
values[0x1]	1849263	1			T4	316		T6	794		T15	40713

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	605610	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35490856

1

T4

5323

T6

12153

T15

145511

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16980959	1			T4	2662		T6	6077		T15	72756
valid_sources[0x01]	16980739	1			T4	2661		T6	6076		T15	72755
valid_sources[0x02]	33068	1			T76	1		T136	817		T520	29
valid_sources[0x03]	34567	1			T152	1		T136	829		T520	45
valid_sources[0x04]	34627	1			T76	1		T136	825		T520	39
valid_sources[0x05]	34038	1			T72	1		T57	1		T152	1
valid_sources[0x06]	33891	1			T76	1		T72	1		T57	2
valid_sources[0x07]	33812	1			T76	3		T136	773		T520	34
valid_sources[0x08]	33785	1			T72	1		T57	2		T152	1
valid_sources[0x09]	34543	1			T57	4		T136	796		T520	27
valid_sources[0x0a]	34387	1			T76	2		T136	763		T520	69
valid_sources[0x0b]	34129	1			T76	2		T57	1		T153	1
valid_sources[0x0c]	34444	1			T136	753		T520	53		T130	167
valid_sources[0x0d]	34462	1			T76	1		T57	3		T153	2
valid_sources[0x0e]	34046	1			T76	1		T57	1		T152	1
valid_sources[0x0f]	34170	1			T72	1		T77	3		T152	3
valid_sources[0x10]	34397	1			T76	1		T72	1		T136	801
valid_sources[0x11]	35185	1			T57	1		T152	1		T136	826
valid_sources[0x12]	33664	1			T76	1		T152	2		T136	839
valid_sources[0x13]	34087	1			T77	5		T153	6		T136	780
valid_sources[0x14]	33686	1			T72	1		T152	1		T153	2
valid_sources[0x15]	35172	1			T72	1		T152	1		T136	812
valid_sources[0x16]	35635	1			T76	4		T57	1		T136	781
valid_sources[0x17]	34129	1			T76	1		T72	1		T57	1
valid_sources[0x18]	35197	1			T76	1		T72	3		T152	3
valid_sources[0x19]	33604	1			T76	1		T57	2		T136	803
valid_sources[0x1a]	34066	1			T76	1		T72	2		T57	1
valid_sources[0x1b]	34420	1			T76	2		T152	1		T136	777
valid_sources[0x1c]	33468	1			T136	800		T520	32		T130	134
valid_sources[0x1d]	35328	1			T72	1		T57	6		T153	3
valid_sources[0x1e]	34132	1			T77	12		T136	768		T520	34
valid_sources[0x1f]	34485	1			T136	789		T520	56		T130	158
valid_sources[0x20]	34135	1			T152	2		T136	740		T520	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23844202

1

T4

1900

T6

4810

T15

78154

values[0x0]

all_enables

biggest_size

9682258

1

T4

3107

T6

6549

T15

26644

values[0x1]

all_enables

biggest_size

205933

1

T76

22

T72

14

T77

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2942708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

465537

1

T73

328

T74

18

T75

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1153077	1			T73	820		T74	45		T75	64
values[0x0]	1100953	1			T73	781		T74	37		T75	59
values[0x1]	1154215	1			T73	794		T74	57		T75	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2278925	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1129320

1

T73

787

T74

41

T75

65

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54077	1			T73	15		T75	1		T117	66
valid_sources[0x01]	52464	1			T73	34		T74	2		T75	2
valid_sources[0x02]	54388	1			T73	18		T74	2		T75	2
valid_sources[0x03]	53274	1			T73	37		T74	2		T117	49
valid_sources[0x04]	53439	1			T73	73		T75	3		T117	32
valid_sources[0x05]	52873	1			T74	9		T75	3		T117	48
valid_sources[0x06]	53661	1			T73	47		T117	39		T368	30
valid_sources[0x07]	53395	1			T73	33		T74	10		T75	6
valid_sources[0x08]	52788	1			T73	17		T74	5		T117	35
valid_sources[0x09]	52761	1			T73	71		T74	3		T75	1
valid_sources[0x0a]	54728	1			T73	35		T74	1		T75	1
valid_sources[0x0b]	52948	1			T117	55		T368	46		T225	1
valid_sources[0x0c]	53368	1			T73	23		T74	1		T75	2
valid_sources[0x0d]	53821	1			T73	39		T117	47		T368	36
valid_sources[0x0e]	53094	1			T73	44		T75	4		T117	34
valid_sources[0x0f]	53030	1			T73	26		T74	1		T117	31
valid_sources[0x10]	52760	1			T73	41		T74	2		T75	10
valid_sources[0x11]	54170	1			T73	73		T75	6		T117	47
valid_sources[0x12]	52083	1			T73	59		T74	3		T117	27
valid_sources[0x13]	52766	1			T73	20		T75	18		T117	41
valid_sources[0x14]	53088	1			T73	37		T117	29		T368	47
valid_sources[0x15]	53741	1			T73	24		T74	1		T117	28
valid_sources[0x16]	53593	1			T73	42		T74	7		T75	13
valid_sources[0x17]	53755	1			T73	14		T75	1		T117	35
valid_sources[0x18]	53131	1			T73	63		T75	1		T117	63
valid_sources[0x19]	53119	1			T73	27		T117	34		T368	57
valid_sources[0x1a]	53799	1			T73	67		T75	2		T117	36
valid_sources[0x1b]	52575	1			T73	65		T74	4		T117	19
valid_sources[0x1c]	52641	1			T74	2		T75	1		T117	41
valid_sources[0x1d]	53864	1			T73	47		T75	6		T117	50
valid_sources[0x1e]	53524	1			T73	84		T117	26		T368	35
valid_sources[0x1f]	53508	1			T73	15		T75	1		T117	34
valid_sources[0x20]	53463	1			T73	25		T74	12		T75	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48469

1

T73

30

T74

2

T75

3

values[0x0]

all_enables

biggest_size

368198

1

T73

261

T74

11

T75

25

values[0x1]

all_enables

biggest_size

48870

1

T73

37

T74

5

T75

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3134928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

510730

1

T73

299

T74

25

T75

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1246128	1			T73	799		T74	62		T75	31
values[0x0]	1152305	1			T73	719		T74	62		T75	28
values[0x1]	1247225	1			T73	790		T74	51		T75	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2406952	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1238706

1

T73

790

T74

51

T75

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56196	1			T73	15		T74	1		T75	5
valid_sources[0x01]	57218	1			T73	42		T74	2		T75	6
valid_sources[0x02]	57553	1			T73	11		T74	2		T75	3
valid_sources[0x03]	57788	1			T73	20		T74	4		T75	8
valid_sources[0x04]	57236	1			T73	76		T74	6		T75	3
valid_sources[0x05]	57565	1			T74	2		T117	91		T368	40
valid_sources[0x06]	56281	1			T73	62		T74	4		T75	3
valid_sources[0x07]	56710	1			T73	45		T74	2		T75	2
valid_sources[0x08]	57119	1			T73	20		T117	36		T368	29
valid_sources[0x09]	56950	1			T73	71		T74	2		T75	5
valid_sources[0x0a]	57686	1			T73	41		T74	6		T117	90
valid_sources[0x0b]	56986	1			T74	4		T117	84		T368	50
valid_sources[0x0c]	57257	1			T73	16		T74	4		T117	80
valid_sources[0x0d]	57168	1			T73	45		T74	3		T75	1
valid_sources[0x0e]	56816	1			T73	32		T74	4		T75	1
valid_sources[0x0f]	56660	1			T73	29		T74	3		T75	1
valid_sources[0x10]	56960	1			T73	28		T74	3		T117	85
valid_sources[0x11]	57480	1			T73	60		T74	5		T117	80
valid_sources[0x12]	58157	1			T73	42		T117	41		T368	36
valid_sources[0x13]	56226	1			T73	7		T74	1		T75	1
valid_sources[0x14]	56079	1			T73	44		T74	5		T117	46
valid_sources[0x15]	57537	1			T73	34		T75	6		T117	59
valid_sources[0x16]	57819	1			T73	25		T74	10		T117	71
valid_sources[0x17]	56667	1			T73	15		T74	3		T117	48
valid_sources[0x18]	56650	1			T73	87		T74	2		T117	80
valid_sources[0x19]	56504	1			T73	25		T74	4		T75	1
valid_sources[0x1a]	56552	1			T73	75		T74	6		T117	63
valid_sources[0x1b]	56614	1			T73	60		T74	3		T75	1
valid_sources[0x1c]	57076	1			T75	3		T117	31		T368	48
valid_sources[0x1d]	56527	1			T73	56		T74	1		T75	2
valid_sources[0x1e]	57917	1			T73	68		T74	3		T117	44
valid_sources[0x1f]	57472	1			T73	10		T74	4		T75	1
valid_sources[0x20]	57497	1			T73	21		T74	2		T117	66

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53445

1

T73

31

T75

1

T117

58

values[0x0]

all_enables

biggest_size

403934

1

T73

233

T74

23

T75

9

values[0x1]

all_enables

biggest_size

53351

1

T73

35

T74

2

T117

49

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2981418	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

472375

1

T73

335

T74

16

T75

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1167860	1			T73	787		T74	43		T75	34
values[0x0]	1116937	1			T73	750		T74	29		T75	42
values[0x1]	1168996	1			T73	757		T74	36		T75	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2307684	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1146109

1

T73

789

T74

39

T75

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53950	1			T73	20		T74	6		T75	3
valid_sources[0x01]	54247	1			T73	44		T74	2		T117	35
valid_sources[0x02]	54557	1			T73	16		T75	3		T117	96
valid_sources[0x03]	54575	1			T73	26		T74	2		T117	56
valid_sources[0x04]	53486	1			T73	76		T117	15		T368	49
valid_sources[0x05]	54463	1			T75	3		T117	41		T368	70
valid_sources[0x06]	53752	1			T73	38		T74	7		T75	3
valid_sources[0x07]	54091	1			T73	30		T117	59		T368	57
valid_sources[0x08]	53594	1			T73	9		T74	1		T75	1
valid_sources[0x09]	53529	1			T73	62		T75	3		T117	41
valid_sources[0x0a]	54952	1			T73	66		T117	55		T368	71
valid_sources[0x0b]	53860	1			T75	3		T117	52		T368	73
valid_sources[0x0c]	54104	1			T73	20		T74	3		T75	2
valid_sources[0x0d]	53601	1			T73	45		T117	93		T368	53
valid_sources[0x0e]	53800	1			T73	48		T75	3		T117	45
valid_sources[0x0f]	54243	1			T73	28		T74	3		T75	1
valid_sources[0x10]	53169	1			T73	47		T117	56		T368	21
valid_sources[0x11]	54133	1			T73	59		T117	47		T368	86
valid_sources[0x12]	53589	1			T73	53		T117	39		T368	19
valid_sources[0x13]	53943	1			T73	5		T117	40		T368	11
valid_sources[0x14]	53264	1			T73	37		T75	1		T117	36
valid_sources[0x15]	54748	1			T73	21		T75	2		T117	30
valid_sources[0x16]	54458	1			T73	42		T117	43		T368	39
valid_sources[0x17]	53841	1			T73	6		T75	3		T117	31
valid_sources[0x18]	53292	1			T73	75		T75	3		T117	62
valid_sources[0x19]	53986	1			T73	34		T117	35		T368	24
valid_sources[0x1a]	53562	1			T73	51		T117	53		T368	43
valid_sources[0x1b]	53425	1			T73	39		T117	41		T368	73
valid_sources[0x1c]	54064	1			T74	11		T117	49		T368	28
valid_sources[0x1d]	54267	1			T73	54		T74	1		T75	1
valid_sources[0x1e]	55356	1			T73	49		T75	2		T117	33
valid_sources[0x1f]	53337	1			T73	19		T75	3		T117	53
valid_sources[0x20]	54482	1			T73	32		T74	3		T75	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49118

1

T73

37

T74

2

T75

2

values[0x0]

all_enables

biggest_size

373691

1

T73

266

T74

13

T75

11

values[0x1]

all_enables

biggest_size

49566

1

T73

32

T74

1

T75

1