Line Coverage for Module :
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
25 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
1 |
1 |
Line Coverage for Module :
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 4 | 66.67 |
CONT_ASSIGN | 32 | 1 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
32 |
0 |
1 |
43 |
0 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
1 |
1 |
Assert Coverage for Module :
tlul_rsp_intg_gen
Assertion Details
DataWidthCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20283 |
20283 |
0 |
0 |
T4 |
9 |
9 |
0 |
0 |
T5 |
9 |
9 |
0 |
0 |
T6 |
9 |
9 |
0 |
0 |
T15 |
9 |
9 |
0 |
0 |
T16 |
9 |
9 |
0 |
0 |
T17 |
9 |
9 |
0 |
0 |
T22 |
9 |
9 |
0 |
0 |
T82 |
9 |
9 |
0 |
0 |
T83 |
9 |
9 |
0 |
0 |
T84 |
9 |
9 |
0 |
0 |
PayLoadWidthCheck
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20283 |
20283 |
0 |
0 |
T4 |
9 |
9 |
0 |
0 |
T5 |
9 |
9 |
0 |
0 |
T6 |
9 |
9 |
0 |
0 |
T15 |
9 |
9 |
0 |
0 |
T16 |
9 |
9 |
0 |
0 |
T17 |
9 |
9 |
0 |
0 |
T22 |
9 |
9 |
0 |
0 |
T82 |
9 |
9 |
0 |
0 |
T83 |
9 |
9 |
0 |
0 |
T84 |
9 |
9 |
0 |
0 |