Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 75.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.12 88.24 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.26 90.91 69.23 88.89 100.00 tl_adapter_host_i_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_gen 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.91 91.30 82.35 90.00 100.00 tl_adapter_host_d_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_gen 100.00 100.00

Line Coverage for Module : tlul_cmd_intg_gen
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN2011100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
ALWAYS4644100.00
CONT_ASSIGN5411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
20 1 1
41 1 1
42 1 1
46 1 1
47 1 1
48 1 1
49 1 1
54 1 1


Assert Coverage for Module : tlul_cmd_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayMaxWidthCheck_A 1986 1986 0 0


PayMaxWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1986 1986 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T22 2 2 0 0
T82 2 2 0 0
T83 2 2 0 0
T84 2 2 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen
Line No.TotalCoveredPercent
TOTAL8675.00
CONT_ASSIGN2011100.00
CONT_ASSIGN41100.00
CONT_ASSIGN42100.00
ALWAYS4644100.00
CONT_ASSIGN5411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
20 1 1
41 0 1
42 0 1
46 1 1
47 1 1
48 1 1
49 1 1
54 1 1


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayMaxWidthCheck_A 993 993 0 0


PayMaxWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN2011100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
ALWAYS4644100.00
CONT_ASSIGN5411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
20 1 1
41 1 1
42 1 1
46 1 1
47 1 1
48 1 1
49 1 1
54 1 1


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayMaxWidthCheck_A 993 993 0 0


PayMaxWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%