Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : csrng
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.27 99.27

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_csrng_0.1/rtl/csrng.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_csrng 99.27 99.27



Module Instance : tb.dut.top_earlgrey.u_csrng

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.27 99.27


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.27 99.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : csrng
TotalCoveredPercent
Totals 65 62 95.38
Total Bits 1790 1777 99.27
Total Bits 0->1 895 889 99.33
Total Bits 1->0 895 888 99.22

Ports 65 62 95.38
Port Bits 1790 1777 99.27
Port Bits 0->1 895 889 99.33
Port Bits 1->0 895 888 99.22

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T6,T15 Yes T4,T6,T15 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T6,T15 Yes T4,T6,T15 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T6,T15 Yes T4,T6,T15 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T15,T84,T40 Yes T15,T84,T40 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T6,T15 Yes T4,T6,T15 INPUT
tl_i.a_address[6:0] Yes Yes *T73,*T74,*T75 Yes T73,T74,T75 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T6,*T15 Yes T4,T6,T15 INPUT
tl_i.a_address[17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T4,*T6,*T15 Yes T4,T6,T15 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T4,*T6,*T15 Yes T4,T6,T15 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T4,*T6,*T15 Yes T4,T6,T15 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T6,*T15 Yes T4,T6,T15 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 INPUT
tl_i.a_valid Yes Yes T4,T6,T15 Yes T4,T6,T15 INPUT
tl_o.a_ready Yes Yes T4,T6,T15 Yes T4,T6,T15 OUTPUT
tl_o.d_error Yes Yes T73,T75,T117 Yes T73,T75,T117 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T15,T84,T40 Yes T15,T84,T40 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T6,T15,T17 Yes T4,T6,T15 OUTPUT
tl_o.d_data[31:0] Yes Yes T6,T15,T17 Yes T4,T6,T15 OUTPUT
tl_o.d_sink Yes Yes T73,T74,T75 Yes T73,T74,T75 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T73,*T117 Yes T72,T73,T74 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T15,*T84,*T40 Yes T15,T84,T40 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T6,T15 Yes T4,T6,T15 OUTPUT
otp_en_csrng_sw_app_read_i[7:0] Yes Yes T4,T5,T6 Yes T5,T6,T17 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T6,T17,T16 Yes T4,T6,T15 INPUT
entropy_src_hw_if_o.es_req Yes Yes T4,T6,T15 Yes T4,T6,T15 OUTPUT
entropy_src_hw_if_i.es_fips Yes Yes T107,T116,T370 Yes T15,T84,T40 INPUT
entropy_src_hw_if_i.es_bits[383:0] Yes Yes T15,T84,T109 Yes T15,T84,T109 INPUT
entropy_src_hw_if_i.es_ack Yes Yes T4,T6,T15 Yes T4,T6,T15 INPUT
cs_aes_halt_i.cs_aes_halt_req Yes Yes T15,T84,T40 Yes T15,T84,T40 INPUT
cs_aes_halt_o.cs_aes_halt_ack Yes Yes T15,T84,T40 Yes T15,T84,T40 OUTPUT
csrng_cmd_i[0].genbits_ready Yes Yes T4,T6,T15 Yes T4,T6,T15 INPUT
csrng_cmd_i[0].csrng_req_bus[31:0] Yes Yes T6,T15,T17 Yes T4,T6,T15 INPUT
csrng_cmd_i[0].csrng_req_valid Yes Yes T4,T6,T15 Yes T4,T6,T15 INPUT
csrng_cmd_i[1].genbits_ready Yes Yes T15,T84,T40 Yes T15,T84,T40 INPUT
csrng_cmd_i[1].csrng_req_bus[31:0] Yes Yes T15,T84,T109 Yes T15,T84,T40 INPUT
csrng_cmd_i[1].csrng_req_valid Yes Yes T15,T84,T40 Yes T15,T84,T40 INPUT
csrng_cmd_o[0].genbits_bus[127:0] Yes Yes T4,T6,T15 Yes T4,T6,T15 OUTPUT
csrng_cmd_o[0].genbits_fips Yes Yes T107,T448,T449 Yes T15,T84,T40 OUTPUT
csrng_cmd_o[0].genbits_valid Yes Yes T4,T6,T15 Yes T4,T6,T15 OUTPUT
csrng_cmd_o[0].csrng_rsp_sts[2:0] No No No OUTPUT
csrng_cmd_o[0].csrng_rsp_ack Yes Yes T4,T6,T15 Yes T4,T6,T15 OUTPUT
csrng_cmd_o[0].csrng_req_ready Yes Yes T15,T84,T234 Yes T15,T84,T234 OUTPUT
csrng_cmd_o[1].genbits_bus[127:0] Yes Yes T15,T84,T40 Yes T15,T84,T109 OUTPUT
csrng_cmd_o[1].genbits_fips No No Yes T448,T449,T451 OUTPUT
csrng_cmd_o[1].genbits_valid Yes Yes T15,T84,T40 Yes T15,T84,T40 OUTPUT
csrng_cmd_o[1].csrng_rsp_sts[2:0] No No No OUTPUT
csrng_cmd_o[1].csrng_rsp_ack Yes Yes T15,T84,T40 Yes T15,T84,T40 OUTPUT
csrng_cmd_o[1].csrng_req_ready Yes Yes T15,T84,T234 Yes T15,T84,T234 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T78,T79,T58 Yes T78,T79,T58 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T79,T296 Yes T78,T79,T296 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T79,T296 Yes T78,T79,T296 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T78,T79,T58 Yes T78,T79,T58 INPUT
alert_rx_i[1].ping_n Yes Yes T78,T79,T81 Yes T78,T79,T81 INPUT
alert_rx_i[1].ping_p Yes Yes T78,T79,T81 Yes T78,T79,T81 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T78,T79,T58 Yes T78,T79,T58 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T78,T79,T58 Yes T78,T79,T58 OUTPUT
intr_cs_cmd_req_done_o Yes Yes T290,T291,T294 Yes T290,T291,T294 OUTPUT
intr_cs_entropy_req_o Yes Yes T298,T290,T291 Yes T298,T290,T291 OUTPUT
intr_cs_hw_inst_exc_o Yes Yes T290,T291,T294 Yes T290,T291,T294 OUTPUT
intr_cs_fatal_err_o Yes Yes T290,T291,T294 Yes T290,T291,T294 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%