Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486226661	54091129	0	0
DepthKnown_A	486226661	486121491	0	0
RvalidKnown_A	486226661	486121491	0	0
WreadyKnown_A	486226661	486121491	0	0
gen_passthru_fifo.paramCheckPass	993	993	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	54091129	0	0
T4	99074	10016	0	0
T5	49632	0	0	0
T6	188457	22925	0	0
T15	797612	104041	0	0
T16	520834	739360	0	0
T17	252179	22351	0	0
T22	475234	12163	0	0
T82	162251	18176	0	0
T83	151787	20317	0	0
T84	330100	42741	0	0
T111	0	40565	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	486121491	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	486121491	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	486121491	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	993	993	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486226661	41797973	0	0
DepthKnown_A	486226661	486121491	0	0
RvalidKnown_A	486226661	486121491	0	0
WreadyKnown_A	486226661	486121491	0	0
gen_passthru_fifo.paramCheckPass	993	993	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	41797973	0	0
T4	99074	7819	0	0
T5	49632	0	0	0
T6	188457	17750	0	0
T15	797612	90413	0	0
T16	520834	733289	0	0
T17	252179	16618	0	0
T22	475234	9308	0	0
T82	162251	15674	0	0
T83	151787	15184	0	0
T84	330100	37834	0	0
T111	0	30540	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	486121491	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	486121491	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	486121491	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	993	993	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486226661	39102976	0	0
DepthKnown_A	486226661	486121491	0	0
RvalidKnown_A	486226661	486121491	0	0
WreadyKnown_A	486226661	486121491	0	0
gen_passthru_fifo.paramCheckPass	993	993	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	39102976	0	0
T4	99074	5463	0	0
T5	49632	0	0	0
T6	188457	12458	0	0
T15	797612	146002	0	0
T16	520834	13320	0	0
T17	252179	12999	0	0
T22	475234	6922	0	0
T82	162251	23644	0	0
T83	151787	8936	0	0
T84	330100	33015	0	0
T111	0	24277	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	486121491	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	486121491	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	486121491	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	993	993	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486226661	33985725	0	0
DepthKnown_A	486226661	486121491	0	0
RvalidKnown_A	486226661	486121491	0	0
WreadyKnown_A	486226661	486121491	0	0
gen_passthru_fifo.paramCheckPass	993	993	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	33985725	0	0
T4	99074	5323	0	0
T5	49632	0	0	0
T6	188457	12153	0	0
T15	797612	145511	0	0
T16	520834	12965	0	0
T17	252179	12590	0	0
T22	475234	6747	0	0
T82	162251	23525	0	0
T83	151787	8658	0	0
T84	330100	32265	0	0
T111	0	23744	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	486121491	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	486121491	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	486121491	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	993	993	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	552420034	82710	0	0
DepthKnown_A	552420034	552303143	0	0
RvalidKnown_A	552420034	552303143	0	0
WreadyKnown_A	552420034	552303143	0	0
gen_passthru_fifo.paramCheckPass	2884	2884	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	82710	0	0
T4	99074	19	0	0
T5	49632	0	0	0
T6	188457	30	0	0
T15	797612	75	0	0
T16	520834	30	0	0
T17	252179	49	0	0
T22	475234	12	0	0
T82	162251	115	0	0
T83	151787	26	0	0
T84	330100	740	0	0
T111	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2884	2884	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	552420034	84710	0	0
DepthKnown_A	552420034	552303143	0	0
RvalidKnown_A	552420034	552303143	0	0
WreadyKnown_A	552420034	552303143	0	0
gen_passthru_fifo.paramCheckPass	2884	2884	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	84710	0	0
T4	99074	19	0	0
T5	49632	0	0	0
T6	188457	30	0	0
T15	797612	75	0	0
T16	520834	30	0	0
T17	252179	49	0	0
T22	475234	12	0	0
T82	162251	115	0	0
T83	151787	26	0	0
T84	330100	740	0	0
T111	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2884	2884	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	552420034	51863	0	0
DepthKnown_A	552420034	552303143	0	0
RvalidKnown_A	552420034	552303143	0	0
WreadyKnown_A	552420034	552303143	0	0
gen_passthru_fifo.paramCheckPass	2884	2884	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	51863	0	0
T4	99074	18	0	0
T5	49632	0	0	0
T6	188457	24	0	0
T15	797612	40	0	0
T16	520834	24	0	0
T17	252179	46	0	0
T22	475234	11	0	0
T82	162251	12	0	0
T83	151787	23	0	0
T84	330100	507	0	0
T111	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2884	2884	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	552420034	51863	0	0
DepthKnown_A	552420034	552303143	0	0
RvalidKnown_A	552420034	552303143	0	0
WreadyKnown_A	552420034	552303143	0	0
gen_passthru_fifo.paramCheckPass	2884	2884	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	51863	0	0
T4	99074	18	0	0
T5	49632	0	0	0
T6	188457	24	0	0
T15	797612	40	0	0
T16	520834	24	0	0
T17	252179	46	0	0
T22	475234	11	0	0
T82	162251	12	0	0
T83	151787	23	0	0
T84	330100	507	0	0
T111	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2884	2884	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	552420034	30847	0	0
DepthKnown_A	552420034	552303143	0	0
RvalidKnown_A	552420034	552303143	0	0
WreadyKnown_A	552420034	552303143	0	0
gen_passthru_fifo.paramCheckPass	2884	2884	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	30847	0	0
T4	99074	1	0	0
T5	49632	0	0	0
T6	188457	6	0	0
T15	797612	35	0	0
T16	520834	6	0	0
T17	252179	3	0	0
T22	475234	1	0	0
T82	162251	103	0	0
T83	151787	3	0	0
T84	330100	233	0	0
T111	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2884	2884	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	552420034	32847	0	0
DepthKnown_A	552420034	552303143	0	0
RvalidKnown_A	552420034	552303143	0	0
WreadyKnown_A	552420034	552303143	0	0
gen_passthru_fifo.paramCheckPass	2884	2884	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	32847	0	0
T4	99074	1	0	0
T5	49632	0	0	0
T6	188457	6	0	0
T15	797612	35	0	0
T16	520834	6	0	0
T17	252179	3	0	0
T22	475234	1	0	0
T82	162251	103	0	0
T83	151787	3	0	0
T84	330100	233	0	0
T111	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552420034	552303143	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2884	2884	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0