Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T52,T55,T53	Yes	T52,T55,T53	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T52,T55,T53	Yes	T52,T55,T53	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	INPUT
tl_i.a_valid	Yes	Yes	T52,T55,T53	Yes	T52,T55,T53	INPUT
tl_o.a_ready	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T77,*T73	Yes	T72,T77,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T52,*T53,*T54	Yes	T52,T53,T54	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T78,T517	Yes	T16,T78,T517	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T16,T78,T79	Yes	T16,T78,T79	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T16,T78,T79	Yes	T16,T78,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T78,T517	Yes	T16,T78,T517	OUTPUT
cio_rx_i	Yes	Yes	T17,T19,T39	Yes	T4,T6,T15	INPUT
cio_tx_o	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T98,T101,T104	Yes	T98,T101,T104	OUTPUT
intr_tx_empty_o	Yes	Yes	T98,T101,T104	Yes	T98,T101,T104	OUTPUT
intr_rx_watermark_o	Yes	Yes	T98,T101,T104	Yes	T98,T101,T104	OUTPUT
intr_tx_done_o	Yes	Yes	T98,T101,T104	Yes	T98,T101,T104	OUTPUT
intr_rx_overflow_o	Yes	Yes	T98,T101,T104	Yes	T98,T101,T104	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_break_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_timeout_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T52,T55,T53	Yes	T52,T55,T53	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T52,T55,T53	Yes	T52,T55,T53	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	INPUT
tl_i.a_valid	Yes	Yes	T52,T55,T53	Yes	T52,T55,T53	INPUT
tl_o.a_ready	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T117,T368	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T77,*T73	Yes	T72,T77,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T52,*T53,*T54	Yes	T52,T53,T54	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T78,T517	Yes	T16,T78,T517	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T16,T78,T79	Yes	T16,T78,T79	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T16,T78,T79	Yes	T16,T78,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T78,T517	Yes	T16,T78,T517	OUTPUT
cio_rx_i	Yes	Yes	T17,T19,T39	Yes	T4,T6,T15	INPUT
cio_tx_o	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T98,T101,T104	Yes	T98,T101,T104	OUTPUT
intr_tx_empty_o	Yes	Yes	T98,T101,T104	Yes	T98,T101,T104	OUTPUT
intr_rx_watermark_o	Yes	Yes	T98,T101,T104	Yes	T98,T101,T104	OUTPUT
intr_tx_done_o	Yes	Yes	T98,T101,T104	Yes	T98,T101,T104	OUTPUT
intr_rx_overflow_o	Yes	Yes	T98,T101,T104	Yes	T98,T101,T104	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_break_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_timeout_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T104,T72,T77	Yes	T104,T72,T77	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T104,T72,T77	Yes	T104,T72,T77	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	INPUT
tl_i.a_valid	Yes	Yes	T104,T58,T72	Yes	T104,T58,T72	INPUT
tl_o.a_ready	Yes	Yes	T104,T58,T72	Yes	T104,T58,T72	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T104,T72,T77	Yes	T104,T72,T77	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T104,T72,T77	Yes	T104,T58,T72	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T104,T72,T77	Yes	T104,T58,T72	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T77,*T73	Yes	T72,T77,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T104,*T72,*T77	Yes	T104,T72,T77	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T104,T58,T72	Yes	T104,T58,T72	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T79,T58	Yes	T78,T79,T58	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T81	Yes	T78,T79,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T81	Yes	T78,T79,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T79,T58	Yes	T78,T79,T58	OUTPUT
cio_rx_i	Yes	Yes	T41,T306,T307	Yes	T19,T24,T41	INPUT
cio_tx_o	Yes	Yes	T72,T77,T306	Yes	T72,T77,T306	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T104,T72,T306	Yes	T104,T72,T306	OUTPUT
intr_tx_empty_o	Yes	Yes	T104,T72,T77	Yes	T104,T72,T77	OUTPUT
intr_rx_watermark_o	Yes	Yes	T104,T306,T307	Yes	T104,T306,T307	OUTPUT
intr_tx_done_o	Yes	Yes	T104,T306,T307	Yes	T104,T306,T307	OUTPUT
intr_rx_overflow_o	Yes	Yes	T104,T306,T307	Yes	T104,T306,T307	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_break_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_timeout_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T104,T137,T72	Yes	T104,T137,T72	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T104,T137,T72	Yes	T104,T137,T72	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	INPUT
tl_i.a_valid	Yes	Yes	T104,T137,T58	Yes	T104,T137,T58	INPUT
tl_o.a_ready	Yes	Yes	T104,T137,T58	Yes	T104,T137,T58	OUTPUT
tl_o.d_error	Yes	Yes	T73,T117,T368	Yes	T73,T74,T117	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T104,T137,T77	Yes	T104,T137,T77	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T104,T137,T72	Yes	T104,T137,T58	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T104,T137,T72	Yes	T104,T137,T58	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T77,*T73	Yes	T72,T77,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T104,*T137,*T72	Yes	T104,T137,T72	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T104,T137,T58	Yes	T104,T137,T58	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T78,T79	Yes	T16,T78,T79	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T16,T78,T79	Yes	T16,T78,T79	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T16,T78,T79	Yes	T16,T78,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T78,T79	Yes	T16,T78,T79	OUTPUT
cio_rx_i	Yes	Yes	T137,T302,T303	Yes	T137,T302,T303	INPUT
cio_tx_o	Yes	Yes	T137,T77,T302	Yes	T137,T77,T302	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T104,T137,T302	Yes	T104,T137,T302	OUTPUT
intr_tx_empty_o	Yes	Yes	T104,T137,T302	Yes	T104,T137,T302	OUTPUT
intr_rx_watermark_o	Yes	Yes	T104,T137,T302	Yes	T104,T137,T302	OUTPUT
intr_tx_done_o	Yes	Yes	T104,T137,T302	Yes	T104,T137,T302	OUTPUT
intr_rx_overflow_o	Yes	Yes	T104,T137,T302	Yes	T104,T137,T302	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_break_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_timeout_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T104,T26,T27	Yes	T104,T26,T27	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T104,T26,T27	Yes	T104,T26,T27	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	INPUT
tl_i.a_valid	Yes	Yes	T104,T26,T58	Yes	T104,T26,T58	INPUT
tl_o.a_ready	Yes	Yes	T104,T26,T58	Yes	T104,T26,T58	OUTPUT
tl_o.d_error	Yes	Yes	T73,T117,T368	Yes	T73,T74,T117	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T104,T26,T27	Yes	T104,T26,T27	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T104,T26,T27	Yes	T104,T26,T58	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T104,T26,T27	Yes	T104,T26,T58	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T77,*T73	Yes	T72,T77,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T117	Yes	T73,T117,T368	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T104,*T26,*T27	Yes	T104,T26,T27	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T104,T26,T58	Yes	T104,T26,T58	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T79,T58	Yes	T78,T79,T58	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T169	Yes	T79,T169,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T169,T81	Yes	T78,T79,T169	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T79,T58	Yes	T78,T79,T58	OUTPUT
cio_rx_i	Yes	Yes	T26,T27,T271	Yes	T26,T27,T271	INPUT
cio_tx_o	Yes	Yes	T26,T27,T72	Yes	T26,T27,T72	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T104,T26,T27	Yes	T104,T26,T27	OUTPUT
intr_tx_empty_o	Yes	Yes	T104,T26,T27	Yes	T104,T26,T27	OUTPUT
intr_rx_watermark_o	Yes	Yes	T104,T26,T27	Yes	T104,T26,T27	OUTPUT
intr_tx_done_o	Yes	Yes	T104,T26,T27	Yes	T104,T26,T27	OUTPUT
intr_rx_overflow_o	Yes	Yes	T104,T26,T27	Yes	T104,T26,T27	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_break_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_timeout_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T104,T288,T297	Yes	T104,T288,T297	OUTPUT

*Tests covering at least one bit in the range