Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T63,T185,T195	Yes	T63,T185,T195	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T63,T185,T195	Yes	T63,T185,T195	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T76,T72,T73	Yes	T76,T72,T73	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T76,T72,T73	Yes	T76,T72,T73	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T39,T63,T196	Yes	T39,T63,T196	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T6,T17,T16	Yes	T4,T6,T15	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T18,T67,T68	Yes	T18,T67,T68	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T6,T17,T16	Yes	T4,T6,T15	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T6,T17,T16	Yes	T4,T6,T15	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T18,T67,T68	Yes	T18,T67,T68	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T6,T17,T16	Yes	T4,T6,T15	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T18,T67,T68	Yes	T18,T67,T68	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T18,T67,T68	Yes	T18,T67,T68	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T67,T68	Yes	T18,T67,T68	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T67,T76,T72	Yes	T67,T76,T72	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T18,*T67,*T68	Yes	T18,T67,T68	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T18,T67,T68	Yes	T18,T67,T68	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T73,T117,T368	Yes	T73,T117,T368	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T73,T117,T368	Yes	T73,T74,T117	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T117,T368	Yes	T73,T74,T117	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T73,T117,T368	Yes	T73,T74,T117	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T73,T117,T368	Yes	T73,T117,T368	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T73,T117,T368	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T73,T117,T368	Yes	T73,T75,T117	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T73,*T117,*T368	Yes	T73,T74,T117	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T231,T232,T233	Yes	T231,T232,T233	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T231,T232,T233	Yes	T231,T232,T233	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T231,T232,T233	Yes	T231,T232,T233	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T231,T232,T233	Yes	T231,T232,T233	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T231,T232,T233	Yes	T231,T232,T233	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T231,*T232,*T233	Yes	T231,T232,T233	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T231,T232,T233	Yes	T231,T232,T233	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T6,T15	Yes	T6,T17,T16	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T231,T232,T233	Yes	T231,T232,T233	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T231,T232,T233	Yes	T231,T232,T233	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T6,T17,T16	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T231,*T232,*T233	Yes	T231,T232,T233	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T15	Yes	T6,T17,T16	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T231,T232,T233	Yes	T231,T232,T233	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T18,T52,T53	Yes	T18,T52,T53	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T58,T59,T60	Yes	T58,T59,T60	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T58,T326,T59	Yes	T58,T326,T59	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T58,T326,T59	Yes	T58,T326,T59	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T58,T59,T60	Yes	T58,T59,T60	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T58,T326,T59	Yes	T58,T326,T59	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T58,T326,T59	Yes	T58,T326,T59	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T58,T326,T59	Yes	T58,T326,T59	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T383,T384,T385	Yes	T383,T384,T385	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T58,T59,T60	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T383,T384,T385	Yes	T58,T59,T383	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T326,*T386,*T383	Yes	T326,T386,T383	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T58,T326,T59	Yes	T58,T326,T59	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_peri_i.d_error	Yes	Yes	T39,T63,T100	Yes	T39,T63,T100	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_peri_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T22,T58,T23	Yes	T22,T58,T23	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T22,T58,T23	Yes	T22,T58,T23	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T22,T58,T23	Yes	T22,T58,T23	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T22,T58,T23	Yes	T22,T58,T23	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T22,T58,T23	Yes	T22,T58,T23	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T22,T58,T23	Yes	T22,T58,T23	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T23,T149,T150	Yes	T23,T149,T150	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T22,T58,T23	Yes	T22,T58,T23	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T22,T58,T23	Yes	T22,T58,T23	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T22,T23,T24	Yes	T22,T23,T24	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T22,T23,T222	Yes	T22,T58,T23	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T22,T23,T24	Yes	T22,T23,T24	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T22,*T23,*T24	Yes	T22,T23,T24	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T22,T58,T23	Yes	T22,T58,T23	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T58,T59,T41	Yes	T58,T59,T41	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T58,T59,T41	Yes	T58,T59,T41	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T58,T59,T41	Yes	T58,T59,T41	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T58,T59,T41	Yes	T58,T59,T41	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T58,T59,T41	Yes	T58,T59,T41	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T58,T59,T41	Yes	T58,T59,T41	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T58,T59,T41	Yes	T58,T59,T41	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T58,T59,T41	Yes	T58,T59,T41	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T73,T117,T368	Yes	T73,T117,T368	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T41,T166,T367	Yes	T41,T166,T367	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T377,T378	Yes	T58,T59,T41	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T41,T166,T367	Yes	T41,T166,T367	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T117,T368	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T73,*T117,*T368	Yes	T73,T74,T75	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T41,*T377,*T378	Yes	T41,T377,T378	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T58,T59,T41	Yes	T58,T59,T41	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T146,T147,T1	Yes	T146,T147,T1	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T146,T147,T1	Yes	T146,T147,T1	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T146,T147,T1	Yes	T146,T147,T1	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T146,T147,T1	Yes	T146,T147,T1	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T1,T104,T28	Yes	T1,T104,T28	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T146,T147,T1	Yes	T146,T147,T1	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T72,*T77,*T73	Yes	T72,T77,T73	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T146,T147,T1	Yes	T146,T147,T1	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T146,T147,T1	Yes	T146,T147,T1	INPUT
tl_usbdev_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T146,T147,T104	Yes	T146,T147,T104	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T146,T147,T104	Yes	T146,T147,T104	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T146,T147,T1	Yes	T146,T147,T1	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T72,*T77,*T73	Yes	T72,T77,T73	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T75,T117	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T146,*T147,*T1	Yes	T146,T147,T1	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T146,T147,T1	Yes	T146,T147,T1	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T6,T17,T16	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T73,*T117,*T368	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T75,T117	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T73,*T75,T117	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_hmac_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T52,T53,T669	Yes	T52,T53,T669	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T52,T53,T669	Yes	T52,T53,T669	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T52,T53,T669	Yes	T52,T53,T669	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T52,T53,T669	Yes	T52,T53,T669	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T52,T53,T669	Yes	T52,T53,T669	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T669,T318,T319	Yes	T669,T318,T319	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T52,T53,T669	Yes	T52,T53,T669	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T52,T53,T669	Yes	T52,T53,T669	INPUT
tl_hmac_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T52,T53,T669	Yes	T52,T53,T669	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T53,T669	Yes	T52,T53,T669	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T52,T53,T669	Yes	T52,T53,T669	INPUT
tl_hmac_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T75,T117	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T73,*T75,*T117	Yes	T73,T74,T75	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T52,*T53,*T669	Yes	T52,T53,T669	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T52,T53,T669	Yes	T52,T53,T669	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T40,T286,T97	Yes	T40,T286,T97	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T40,T109,T286	Yes	T40,T109,T286	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T40,T109,T286	Yes	T40,T109,T286	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T40,T286,T97	Yes	T40,T286,T97	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T40,T109,T286	Yes	T40,T109,T286	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T57,*T73,*T74	Yes	T57,T73,T74	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T286,T97,T197	Yes	T286,T97,T197	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T40,T109,T286	Yes	T40,T109,T286	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T40,T109,T286	Yes	T40,T109,T286	INPUT
tl_kmac_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T117	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T40,T109,T286	Yes	T40,T109,T286	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T40,T109,T286	Yes	T40,T109,T286	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T40,T109,T286	Yes	T286,T97,T199	INPUT
tl_kmac_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T57,*T73,*T117	Yes	T57,T73,T74	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T40,*T109,*T286	Yes	T286,T97,T199	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T40,T109,T286	Yes	T40,T109,T286	INPUT
tl_aes_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T84,T109,T667	Yes	T84,T109,T667	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T84,T109,T667	Yes	T84,T109,T667	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T15,T84,T109	Yes	T15,T84,T109	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T84,T109,T667	Yes	T84,T109,T667	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T15,T84,T109	Yes	T15,T84,T109	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T15,T84,T109	Yes	T15,T84,T109	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T15,T84,T109	Yes	T15,T84,T109	INPUT
tl_aes_i.d_error	Yes	Yes	T73,T117,T368	Yes	T73,T75,T117	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T15,T84,T109	Yes	T15,T84,T109	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T84,T109	Yes	T15,T84,T109	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T15,T84,T667	Yes	T15,T84,T109	INPUT
tl_aes_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T117	Yes	T72,T73,T74	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T15,*T84,*T109	Yes	T15,T84,T109	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T15,T84,T109	Yes	T15,T84,T109	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T73,*T75,*T117	Yes	T73,T75,T117	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T73,T117,T368	Yes	T73,T74,T117	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T15,T17	Yes	T4,T6,T15	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T6,T15,T17	Yes	T4,T6,T15	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T73,*T117,*T368	Yes	T73,T117,T368	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T73,T117,T368	Yes	T73,T75,T117	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T15,*T84,*T40	Yes	T15,T84,T40	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_csrng_i.d_error	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T15,T17	Yes	T4,T6,T15	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T6,T15,T17	Yes	T4,T6,T15	INPUT
tl_csrng_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T117	Yes	T72,T73,T74	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T15,*T84,*T40	Yes	T15,T84,T40	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T73,*T75,*T117	Yes	T73,T75,T117	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_edn0_i.d_error	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T15,T17	Yes	T4,T6,T15	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T6,T15,T17	Yes	T4,T6,T15	INPUT
tl_edn0_i.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T73,*T117,*T368	Yes	T73,T75,T117	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T15,*T84,*T40	Yes	T15,T84,T40	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_edn1_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T73,T117,T368	Yes	T73,T117,T368	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	INPUT
tl_edn1_i.d_error	Yes	Yes	T73,T117,T368	Yes	T73,T74,T75	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	INPUT
tl_edn1_i.d_sink	Yes	Yes	T73,T74,T117	Yes	T73,T74,T75	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T73,*T117,*T368	Yes	T73,T74,T75	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T73,T117,T368	Yes	T73,T117,T368	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T15,*T84,*T40	Yes	T15,T84,T40	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T15,T84,T40	Yes	T15,T84,T40	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T5,T6,T22	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T6,T22,T16	Yes	T6,T22,T16	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T22,T16	Yes	T6,T22,T16	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T6,T22,T16	Yes	T6,T22,T16	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T6,T22,T16	Yes	T6,T22,T16	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T6,T22,T16	Yes	T6,T22,T16	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T73,*T75,*T117	Yes	T73,T75,T117	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T6,T22,T16	Yes	T6,T22,T16	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T6,T22,T16	Yes	T6,T22,T16	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T6,T22,T16	Yes	T6,T22,T16	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T22,T16	Yes	T6,T22,T16	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T6,T22,T16	Yes	T6,T22,T16	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T117	Yes	T73,T74,T75	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T6,*T22,*T16	Yes	T6,T22,T16	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T6,T22,T16	Yes	T6,T22,T16	INPUT
tl_otbn_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T15,T82,T84	Yes	T15,T82,T84	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T15,T82,T84	Yes	T15,T82,T84	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T15,T82,T84	Yes	T15,T82,T84	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T15,T82,T84	Yes	T15,T82,T84	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T15,T82,T84	Yes	T15,T82,T84	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T76,*T57,*T152	Yes	T76,T57,T152	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T15,T82,T84	Yes	T15,T82,T84	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T15,T82,T84	Yes	T15,T82,T84	INPUT
tl_otbn_i.d_error	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T15,T82,T84	Yes	T15,T82,T84	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T82,T84	Yes	T15,T82,T84	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T15,T82,T84	Yes	T15,T82,T84	INPUT
tl_otbn_i.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T76,*T57,*T152	Yes	T76,T57,T152	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T15,*T82,*T84	Yes	T15,T82,T84	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T15,T82,T84	Yes	T15,T82,T84	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T40,T109,T52	Yes	T40,T109,T52	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T40,T109,T52	Yes	T40,T109,T52	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T40,T109,T52	Yes	T40,T109,T52	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T40,T109,T52	Yes	T40,T109,T52	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T40,T109,T52	Yes	T40,T109,T52	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T40,T109,T52	Yes	T40,T109,T52	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T40,T109,T52	Yes	T40,T109,T52	INPUT
tl_keymgr_i.d_error	Yes	Yes	T73,T74,T117	Yes	T73,T74,T75	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T40,T109,T55	Yes	T40,T109,T55	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T40,T109,T52	Yes	T40,T109,T52	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T40,T109,T52	Yes	T40,T109,T52	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T117	Yes	T73,T74,T75	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T40,*T109,*T52	Yes	T40,T109,T52	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T40,T109,T52	Yes	T40,T109,T52	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T6,T15,T82	Yes	T6,T15,T82	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T6,T15,T82	Yes	T6,T15,T82	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T73,*T75,*T117	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T75,T117	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T231,*T440,*T73	Yes	T231,T440,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T75,T117	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T185,T272,T273	Yes	T185,T272,T273	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T185,T49,T50	Yes	T52,T53,T54	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T185,T49,T50	Yes	T52,T53,T54	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T117	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T73,*T117,*T368	Yes	T231,T440,T73	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T185,*T183,*T112	Yes	T185,T441,T183	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range