SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.27 | 94.12 | 89.29 | 99.75 | 100.00 | 68.18 | u_rv_core_ibex |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 14 | 14 | 100.00 |
Total Bits 0->1 | 7 | 7 | 100.00 |
Total Bits 1->0 | 7 | 7 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 14 | 14 | 100.00 |
Port Bits 0->1 | 7 | 7 | 100.00 |
Port Bits 1->0 | 7 | 7 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | INPUT |
esc_req_o | Yes | Yes | T83,T230,T39 | Yes | T83,T230,T39 | OUTPUT |
esc_rx_o.resp_n | Yes | Yes | T16,T83,T230 | Yes | T16,T83,T230 | OUTPUT |
esc_rx_o.resp_p | Yes | Yes | T16,T83,T230 | Yes | T16,T83,T230 | OUTPUT |
esc_tx_i.esc_n | Yes | Yes | T16,T83,T230 | Yes | T16,T83,T230 | INPUT |
esc_tx_i.esc_p | Yes | Yes | T16,T83,T230 | Yes | T16,T83,T230 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 14 | 14 | 100.00 |
Total Bits 0->1 | 7 | 7 | 100.00 |
Total Bits 1->0 | 7 | 7 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 14 | 14 | 100.00 |
Port Bits 0->1 | 7 | 7 | 100.00 |
Port Bits 1->0 | 7 | 7 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | INPUT |
esc_req_o | Yes | Yes | T83,T230,T39 | Yes | T83,T230,T39 | OUTPUT |
esc_rx_o.resp_n | Yes | Yes | T16,T83,T230 | Yes | T16,T83,T230 | OUTPUT |
esc_rx_o.resp_p | Yes | Yes | T16,T83,T230 | Yes | T16,T83,T230 | OUTPUT |
esc_tx_i.esc_n | Yes | Yes | T16,T83,T230 | Yes | T16,T83,T230 | INPUT |
esc_tx_i.esc_p | Yes | Yes | T16,T83,T230 | Yes | T16,T83,T230 | INPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |