dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[22].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[0].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[1].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[2].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[3].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[4].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[5].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[6].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[7].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[8].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[9].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[10].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[11].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[12].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[13].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[14].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[15].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[16].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[17].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[18].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[19].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[20].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT19,T157,T158
10CoveredT36,T37,T38
11CoveredT36,T38,T139

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT29,T30,T43
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT19,T12,T13
10CoveredT43,T44,T45
11CoveredT4,T5,T6

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT43,T44,T45
01CoveredT4,T5,T6
10CoveredT43,T44,T45

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT43,T44,T45
11CoveredT43,T44,T45

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT4,T5,T6
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT19,T43,T44
1CoveredT4,T5,T6

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT19,T43,T44
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T19,T43,T44


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T25,T26
01CoveredT25,T26,T27
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT25,T34,T9
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T25,T34
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T25,T34
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T25,T26
01CoveredT25,T26,T27
10CoveredT36,T38,T139
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT25,T26,T27
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T26

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T25,T26
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T25,T26

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T26

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T25,T26
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T25,T105
01CoveredT25,T105,T138
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT25,T105,T138
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T105

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T25,T105
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T25,T105

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T105

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T41,T42

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T25,T105
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T24,T41,T42
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT25,T76,T72
01CoveredT19,T25,T34
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT19,T25,T34
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T25,T34
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T25,T34
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT25,T137,T76
01CoveredT19,T25,T137
10CoveredT36,T38,T139
11CoveredT36,T38,T139

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT19,T25,T34
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T25,T34
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T25,T34
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT25,T137,T76
01CoveredT19,T25,T137
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT19,T25,T137
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T137

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T25,T137
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T25,T137

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T137

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T25,T137
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T25,T76
01CoveredT19,T25,T34
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT25,T34,T9
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT25,T34,T9

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT25,T34,T9
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT25,T34,T9

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT25,T34,T9

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T25,T34,T9
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T25,T76
01CoveredT19,T25,T34
10CoveredT37,T38,T139
11CoveredT37,T38,T139

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT25,T34,T9
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT25,T34,T190

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT25,T34,T190
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT25,T34,T190

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT25,T34,T190

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT46,T47,T48

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T25,T34,T190
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T46,T47,T48
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T25,T76
01CoveredT25,T34,T190
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT25,T34,T35
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T25,T34
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T25,T34
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT76,T72,T77
01CoveredT19,T24,T41
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT22,T19,T23
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T41,T20

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T41,T20
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T41,T20

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T41,T20

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T41,T42

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T41,T20
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T24,T41,T42
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T76,T72
01CoveredT22,T19,T23
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT24,T41,T21
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT41,T20,T21

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT41,T20,T21
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT41,T20,T21

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT41,T20,T21

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT22,T23,T24

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T41,T20,T21
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT76,T72,T77
01CoveredT19,T21,T36
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT19,T21,T36
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T20,T21

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T20,T21
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T20,T21

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T20,T21

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T20,T21
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T157,T76
01CoveredT22,T157,T158
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT41,T42,T36
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T41,T20

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T41,T20
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T41,T20

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T41,T20

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT22,T23,T24

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T41,T20
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T76,T72
01CoveredT19,T24,T41
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT36,T38,T139
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT20,T36,T37

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT20,T36,T37
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT20,T36,T37

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT20,T36,T37

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T41,T42

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T20,T36,T37
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T24,T41,T42
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T76,T72
01CoveredT4,T6,T15
10CoveredT37,T38,T139
11CoveredT37,T38,T139

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT4,T6,T15
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT4,T6,T15

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT4,T6,T15
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T15

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT4,T6,T15

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T41,T42

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T15
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T24,T41,T42
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T157,T25
01CoveredT157,T25,T158
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT25,T34,T35
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T25,T34
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T41,T42

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T25,T34
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T24,T41,T42
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T25,T2
01CoveredT19,T1,T25
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT19,T25,T34
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T25,T34
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T25,T34
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT157,T25,T76
01CoveredT19,T157,T25
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT19,T25,T34
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT19,T25,T34
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T19,T25,T34
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T25,T76
01CoveredT19,T25,T29
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT25,T191,T34
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT25,T191,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT25,T191,T34
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT25,T191,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT25,T191,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T25,T191,T34
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T25,T105
01CoveredT19,T25,T105
10CoveredT36,T37,T139
11CoveredT36,T37,T139

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT25,T105,T138
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT25,T105,T138

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT25,T105,T138
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT25,T105,T138

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT25,T105,T138

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T25,T105,T138
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT36,T37,T38
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT36,T37,T38
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT19,T192,T25
01CoveredT19,T192,T25
10CoveredT36,T37,T38
11CoveredT37,T38,T139

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T37,T38
10CoveredT25,T105,T138
11CoveredT36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT25,T105,T138

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT36,T37,T38
01CoveredT4,T5,T6
10CoveredT36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT25,T105,T138
11CoveredT36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT25,T105,T138

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T37,T38
11CoveredT25,T105,T138

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T36,T37,T38


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T25,T105,T138
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T36,T37,T38
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 993 993 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 993 993 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T22 1 1 0 0
T82 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%