Unified Coverage Report :: Module Instance :: tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T19,T157,T158
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T38,T139

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T29,T30,T43
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T12,T13
1	0	Covered	T43,T44,T45
1	1	Covered	T4,T5,T6

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T43,T44,T45
0	1	Covered	T4,T5,T6
1	0	Covered	T43,T44,T45

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T43,T44,T45
1	1	Covered	T43,T44,T45

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T4,T5,T6
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T19,T43,T44
1	Covered	T4,T5,T6

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T43,T44
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T19,T43,T44



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T25,T26
0	1	Covered	T25,T26,T27
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T34,T9
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T34
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T25,T34
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T25,T26
0	1	Covered	T25,T26,T27
1	0	Covered	T36,T38,T139
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T26,T27
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T26

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T26
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T25,T26

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T26

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T25,T26
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T25,T105
0	1	Covered	T25,T105,T138
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T105,T138
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T105

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T105
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T25,T105

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T105

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T41,T42

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T25,T105
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T41,T42
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T76,T72
0	1	Covered	T19,T25,T34
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T34
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T34
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T25,T34
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T137,T76
0	1	Covered	T19,T25,T137
1	0	Covered	T36,T38,T139
1	1	Covered	T36,T38,T139

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T34
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T34
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T25,T34
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T137,T76
0	1	Covered	T19,T25,T137
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T137
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T137

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T137
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T25,T137

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T137

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T25,T137
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T25,T76
0	1	Covered	T19,T25,T34
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T34,T9
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T25,T34,T9

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T34,T9
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T34,T9

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T25,T34,T9

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T25,T34,T9
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T25,T76
0	1	Covered	T19,T25,T34
1	0	Covered	T37,T38,T139
1	1	Covered	T37,T38,T139

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T34,T9
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T25,T34,T190

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T34,T190
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T34,T190

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T25,T34,T190

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T46,T47,T48

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T25,T34,T190
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T46,T47,T48
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T25,T76
0	1	Covered	T25,T34,T190
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T34,T35
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T34
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T25,T34
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T76,T72,T77
0	1	Covered	T19,T24,T41
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T22,T19,T23
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T41,T20

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T41,T20
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T41,T20

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T41,T20

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T41,T42

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T41,T20
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T41,T42
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T76,T72
0	1	Covered	T22,T19,T23
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T24,T41,T21
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T41,T20,T21

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T41,T20,T21
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T41,T20,T21

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T41,T20,T21

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T23,T24

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T41,T20,T21
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T76,T72,T77
0	1	Covered	T19,T21,T36
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T21,T36
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T20,T21

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T20,T21
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T20,T21

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T20,T21

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T157,T76
0	1	Covered	T22,T157,T158
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T41,T42,T36
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T41,T20

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T41,T20
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T41,T20

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T41,T20

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T23,T24

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T41,T20
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T76,T72
0	1	Covered	T19,T24,T41
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T36,T38,T139
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T20,T36,T37

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T20,T36,T37
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T20,T36,T37

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T20,T36,T37

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T41,T42

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T20,T36,T37
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T41,T42
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T76,T72
0	1	Covered	T4,T6,T15
1	0	Covered	T37,T38,T139
1	1	Covered	T37,T38,T139

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T4,T6,T15
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T6,T15

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T4,T6,T15
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T15

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T6,T15

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T41,T42

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T15
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T41,T42
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T157,T25
0	1	Covered	T157,T25,T158
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T34,T35
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T34
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T41,T42

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T25,T34
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T41,T42
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T25,T2
0	1	Covered	T19,T1,T25
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T34
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T34
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T25,T34
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T157,T25,T76
0	1	Covered	T19,T157,T25
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T34
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T19,T25,T34
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T25,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T19,T25,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T19,T25,T34
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T25,T76
0	1	Covered	T19,T25,T29
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T191,T34
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T25,T191,T34

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T191,T34
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T191,T34

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T25,T191,T34

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T25,T191,T34
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T25,T105
0	1	Covered	T19,T25,T105
1	0	Covered	T36,T37,T139
1	1	Covered	T36,T37,T139

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T105,T138
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T25,T105,T138

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T105,T138
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T105,T138

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T25,T105,T138

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T25,T105,T138
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T36,T37,T38
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T192,T25
0	1	Covered	T19,T192,T25
1	0	Covered	T36,T37,T38
1	1	Covered	T37,T38,T139

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T105,T138
1	1	Covered	T36,T37,T38

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T25,T105,T138

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T25,T105,T138
1	1	Covered	T36,T37,T38

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T105,T138

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T37,T38
1	1	Covered	T25,T105,T138

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T36,T37,T38



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T25,T105,T138
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	993	993	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	993	993
T4	1	1
T5	1	1
T6	1	1
T15	1	1
T16	1	1
T17	1	1
T22	1	1
T82	1	1
T83	1	1
T84	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[22].u_dio_pad

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[0].u_mio_pad

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[1].u_mio_pad