Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_main_o.d_error	Yes	Yes	T39,T63,T100	Yes	T39,T63,T100	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_main_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T52,T55,T53	Yes	T52,T55,T53	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T52,T55,T53	Yes	T52,T55,T53	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T52,T55,T53	Yes	T52,T55,T53	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
tl_uart0_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
tl_uart0_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T117,T368	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T72,*T77,*T73	Yes	T72,T77,T73	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T52,*T53,*T54	Yes	T52,T53,T54	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T104,T72,T77	Yes	T104,T72,T77	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T104,T72,T77	Yes	T104,T72,T77	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T104,T58,T72	Yes	T104,T58,T72	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T104,T58,T72	Yes	T104,T58,T72	INPUT
tl_uart1_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T104,T72,T77	Yes	T104,T72,T77	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T104,T72,T77	Yes	T104,T58,T72	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T104,T72,T77	Yes	T104,T58,T72	INPUT
tl_uart1_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T72,*T77,*T73	Yes	T72,T77,T73	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T104,*T72,*T77	Yes	T104,T72,T77	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T104,T58,T72	Yes	T104,T58,T72	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T104,T137,T72	Yes	T104,T137,T72	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T104,T137,T72	Yes	T104,T137,T72	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T104,T137,T58	Yes	T104,T137,T58	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T104,T137,T58	Yes	T104,T137,T58	INPUT
tl_uart2_i.d_error	Yes	Yes	T73,T117,T368	Yes	T73,T74,T117	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T104,T137,T77	Yes	T104,T137,T77	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T104,T137,T72	Yes	T104,T137,T58	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T104,T137,T72	Yes	T104,T137,T58	INPUT
tl_uart2_i.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T72,*T77,*T73	Yes	T72,T77,T73	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T104,*T137,*T72	Yes	T104,T137,T72	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T104,T137,T58	Yes	T104,T137,T58	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T104,T26,T27	Yes	T104,T26,T27	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T104,T26,T27	Yes	T104,T26,T27	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T104,T26,T58	Yes	T104,T26,T58	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T104,T26,T58	Yes	T104,T26,T58	INPUT
tl_uart3_i.d_error	Yes	Yes	T73,T117,T368	Yes	T73,T74,T117	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T104,T26,T27	Yes	T104,T26,T27	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T104,T26,T27	Yes	T104,T26,T58	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T104,T26,T27	Yes	T104,T26,T58	INPUT
tl_uart3_i.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T72,*T77,*T73	Yes	T72,T77,T73	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T73,T74,T117	Yes	T73,T117,T368	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T104,*T26,*T27	Yes	T104,T26,T27	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T104,T26,T58	Yes	T104,T26,T58	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T190,T367,T308	Yes	T190,T367,T308	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T190,T367,T308	Yes	T190,T367,T308	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T58,T222,T190	Yes	T58,T222,T190	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T58,T222,T190	Yes	T58,T222,T190	INPUT
tl_i2c0_i.d_error	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T190,T308,T309	Yes	T190,T308,T309	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T222,T190,T296	Yes	T58,T222,T190	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T222,T190,T296	Yes	T58,T222,T190	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T75,T117	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T73,*T75,*T117	Yes	T73,T74,T75	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T190,*T367,*T308	Yes	T190,T367,T308	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T58,T222,T190	Yes	T58,T222,T190	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T292,T293,T367	Yes	T292,T293,T367	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T292,T293,T367	Yes	T292,T293,T367	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T58,T292,T222	Yes	T58,T292,T222	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T58,T292,T222	Yes	T58,T292,T222	INPUT
tl_i2c1_i.d_error	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T292,T293,T290	Yes	T292,T293,T290	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T292,T222,T296	Yes	T58,T292,T222	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T292,T222,T296	Yes	T58,T292,T222	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T117,T368	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T73,*T117,*T368	Yes	T73,T74,T75	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T292,*T293,*T367	Yes	T292,T293,T367	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T58,T292,T222	Yes	T58,T292,T222	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T192,T310,T304	Yes	T192,T310,T304	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T192,T310,T304	Yes	T192,T310,T304	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T192,T58,T222	Yes	T192,T58,T222	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T192,T58,T222	Yes	T192,T58,T222	INPUT
tl_i2c2_i.d_error	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T192,T310,T304	Yes	T192,T310,T304	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T192,T222,T310	Yes	T192,T58,T222	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T192,T222,T310	Yes	T192,T58,T222	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T73,T74,T117	Yes	T73,T74,T75	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T117	Yes	T73,T74,T75	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T192,*T310,*T304	Yes	T192,T310,T304	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T192,T58,T222	Yes	T192,T58,T222	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T191,T57,T322	Yes	T191,T57,T322	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T191,T57,T322	Yes	T191,T57,T322	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T58,T191,T57	Yes	T58,T191,T57	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T58,T191,T57	Yes	T58,T191,T57	INPUT
tl_pattgen_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T191,T57,T322	Yes	T191,T57,T322	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T191,T57,T322	Yes	T58,T191,T57	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T191,T57,T322	Yes	T58,T191,T57	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T57,T73,T117	Yes	T57,T73,T74	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T191,*T57,*T322	Yes	T191,T57,T322	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T58,T191,T57	Yes	T58,T191,T57	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T105,T138,T668	Yes	T105,T138,T668	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T105,T138,T668	Yes	T105,T138,T668	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T105,T138,T58	Yes	T105,T138,T58	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T105,T138,T58	Yes	T105,T138,T58	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T105,T138,T668	Yes	T105,T138,T668	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T105,T138,T668	Yes	T105,T138,T58	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T105,T138,T668	Yes	T105,T138,T58	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	T73,*T74,*T117	Yes	T73,T74,T75	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T105,*T138,*T668	Yes	T105,T138,T668	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T105,T138,T58	Yes	T105,T138,T58	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_gpio_i.d_error	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T25,T34,T35	Yes	T25,T34,T35	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T25,T34,T668	Yes	T25,T105,T138	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T25,T34,T668	Yes	T25,T105,T138	INPUT
tl_gpio_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T73,*T75,*T117	Yes	T73,T74,T75	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T6,*T17,*T16	Yes	T4,T6,T15	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T22,T18,T68	Yes	T22,T18,T68	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T22,T18,T68	Yes	T22,T18,T68	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T22,T18,T68	Yes	T22,T18,T68	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T22,T18,T68	Yes	T22,T18,T68	INPUT
tl_spi_device_i.d_error	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T22,T18,T68	Yes	T22,T18,T68	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T22,T18,T68	Yes	T22,T18,T68	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T22,T18,T68	Yes	T22,T18,T68	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T75,T117	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T73,*T75,*T117	Yes	T73,T74,T75	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T22,*T18,*T68	Yes	T22,T18,T68	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T22,T18,T68	Yes	T22,T18,T68	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T4,T105,T138	Yes	T4,T105,T138	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T4,T105,T138	Yes	T4,T105,T138	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T4,T105,T138	Yes	T4,T105,T138	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T4,T105,T138	Yes	T4,T105,T138	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T4,T340,T229	Yes	T4,T340,T229	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T105,T138	Yes	T4,T105,T138	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T4,T105,T138	Yes	T4,T105,T138	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T75,T117	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T73,*T117,*T368	Yes	T73,T74,T75	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T4,*T105,*T138	Yes	T4,T105,T138	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T4,T105,T138	Yes	T4,T105,T138	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T17,T16	Yes	T6,T17,T16	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T6,T17,T16	Yes	T6,T17,T16	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T6,T17,T16	Yes	T6,T17,T16	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T6,T17,T16	Yes	T6,T17,T16	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T17,T16	Yes	T6,T17,T16	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T17,T16	Yes	T6,T17,T16	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T6,T17,T16	Yes	T6,T17,T16	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T73,*T75,*T117	Yes	T73,T74,T75	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T6,*T17,*T16	Yes	T6,T17,T16	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T6,T17,T16	Yes	T6,T17,T16	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T75,T117	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T17,T16	Yes	T4,T6,T15	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T6,T17,T16	Yes	T4,T6,T15	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T56,T55,T196	Yes	T56,T55,T196	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T111,T56,T109	Yes	T111,T56,T109	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T56,T196,T656	Yes	T56,T196,T656	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T56,T39	Yes	T4,T6,T15	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T17,T56,T39	Yes	T4,T6,T15	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T73,T74,T117	Yes	T73,T74,T75	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T117	Yes	T72,T73,T74	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T56,*T55,*T196	Yes	T56,T55,T196	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T57,*T73,*T75	Yes	T57,T73,T74	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T73,T74,T117	Yes	T73,T74,T75	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T18,*T68,*T154	Yes	T18,T68,T154	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T40,*T109,*T18	Yes	T40,T109,T18	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T57,T73,T74	Yes	T57,T73,T74	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T57,T73,T75	Yes	T57,T73,T75	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T57,T73,T74	Yes	T57,T73,T74	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T6,T15	Yes	T6,T17,T16	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T57,T73,T74	Yes	T57,T73,T74	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T57,T73,T74	Yes	T57,T73,T74	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T6,T17,T16	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T57,T73,*T74	Yes	T57,T73,T74	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T15	Yes	T6,T17,T16	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T57,T73,T74	Yes	T57,T73,T74	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T18,T52,T62	Yes	T18,T52,T62	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T18,T52,T62	Yes	T18,T52,T62	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T18,T52,T62	Yes	T18,T52,T62	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T18,T52,T62	Yes	T18,T52,T62	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T18,T52,T62	Yes	T18,T52,T62	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T62,T344,T243	Yes	T62,T58,T344	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T18,T52,T62	Yes	T18,T52,T62	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T57,*T232,*T233	Yes	T57,T232,T233	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T73,T75,T117	Yes	T73,T75,T117	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T18,*T62,*T185	Yes	T18,T52,T62	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T18,T52,T62	Yes	T18,T52,T62	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T73,T74,T117	Yes	T73,T74,T117	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T52,T54	Yes	T6,T52,T54	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T52,T54	Yes	T6,T52,T54	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T6,T17,T39	Yes	T4,T6,T15	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T73,*T117,*T368	Yes	T73,T74,T75	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T117	Yes	T73,T74,T75	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T6,*T17,*T39	Yes	T4,T6,T15	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T73,T74,T117	Yes	T73,T74,T75	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T75,T117	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T16,*T83,*T230	Yes	T16,T83,T230	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T183,T112,T184	Yes	T183,T112,T184	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T49,T50,T183	Yes	T52,T53,T54	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T49,T50,T183	Yes	T52,T53,T54	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T73,*T75,*T117	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T183,*T112,*T184	Yes	T441,T183,T112	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T6,T17,T16	Yes	T6,T17,T16	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T17,T39	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T17,T16,T83	Yes	T17,T16,T83	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T17,T16	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T17,T16,T83	Yes	T17,T16,T83	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T76,*T152,*T153	Yes	T76,T152,T153	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T15	Yes	T4,T6,T15	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T440,T673	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T16,*T83,*T230	Yes	T16,T83,T230	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T16,T83,T230	Yes	T16,T83,T230	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T17,T157,T1	Yes	T17,T157,T1	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T17,T157,T1	Yes	T17,T157,T1	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T17,T157,T1	Yes	T17,T157,T1	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T17,T157,T1	Yes	T17,T157,T1	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T117	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T17,T157,T1	Yes	T17,T157,T1	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T157,T1	Yes	T17,T157,T1	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T17,T157,T195	Yes	T17,T157,T1	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T72,*T77,*T73	Yes	T72,T77,T73	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T17,*T157,*T1	Yes	T17,T157,T1	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T17,T157,T1	Yes	T17,T157,T1	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T73,T117,T368	Yes	T73,T117,T368	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T72	Yes	T1,T2,T72	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T117	Yes	T72,T73,T74	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T117	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T105,*T2	Yes	T1,T105,T2	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T18,*T68,*T76	Yes	T18,T68,T76	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T76,T72,T77	Yes	T76,T72,T77	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
tl_ast_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T17,T16	Yes	T4,T6,T15	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T6,T17,T16	Yes	T4,T6,T15	INPUT
tl_ast_i.d_sink	Yes	Yes	T73,T75,T117	Yes	T73,T74,T75	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T117	Yes	T73,T74,T75	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T73,*T75,*T117	Yes	T73,T74,T75	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range