SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
85.25 | 85.25 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.top_earlgrey.u_otp_ctrl | 85.45 | 85.45 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
85.45 | 85.45 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
85.45 | 85.45 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
93.34 | 90.68 | 89.34 | 100.00 | top_earlgrey |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 164 | 142 | 86.59 |
Total Bits | 11012 | 9388 | 85.25 |
Total Bits 0->1 | 5506 | 4708 | 85.51 |
Total Bits 1->0 | 5506 | 4680 | 85.00 |
Ports | 164 | 142 | 86.59 |
Port Bits | 11012 | 9388 | 85.25 |
Port Bits 0->1 | 5506 | 4708 | 85.51 |
Port Bits 1->0 | 5506 | 4680 | 85.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | INPUT |
clk_edn_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_edn_ni | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | INPUT |
edn_o.edn_req | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT |
edn_i.edn_bus[31:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
edn_i.edn_fips | No | No | Yes | T164,T110,T165 | INPUT | |
edn_i.edn_ack | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
core_tl_i.d_ready | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
core_tl_i.a_user.data_intg[6:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
core_tl_i.a_user.cmd_intg[6:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
core_tl_i.a_user.instr_type[3:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
core_tl_i.a_user.rsvd[4:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_data[31:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
core_tl_i.a_mask[3:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
core_tl_i.a_address[11:0] | Yes | Yes | *T73,*T74,*T75 | Yes | T73,T74,T75 | INPUT |
core_tl_i.a_address[15:12] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_address[17:16] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
core_tl_i.a_address[19:18] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_address[20] | Yes | Yes | *T4,*T6,*T15 | Yes | T4,T6,T15 | INPUT |
core_tl_i.a_address[29:21] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_address[30] | Yes | Yes | *T4,*T6,*T15 | Yes | T4,T6,T15 | INPUT |
core_tl_i.a_address[31] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_source[5:0] | Yes | Yes | *T18,*T68,*T76 | Yes | T18,T68,T76 | INPUT |
core_tl_i.a_source[7:6] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_size[1:0] | Yes | Yes | T73,T74,T75 | Yes | T73,T74,T75 | INPUT |
core_tl_i.a_param[2:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_opcode[2:0] | Yes | Yes | T76,T72,T77 | Yes | T76,T72,T77 | INPUT |
core_tl_i.a_valid | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
core_tl_o.a_ready | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT |
core_tl_o.d_error | Yes | Yes | T73,T74,T117 | Yes | T73,T74,T75 | OUTPUT |
core_tl_o.d_user.data_intg[6:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT |
core_tl_o.d_user.rsp_intg[6:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT |
core_tl_o.d_data[31:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT |
core_tl_o.d_sink | Yes | Yes | T73,T75,T117 | Yes | T73,T74,T75 | OUTPUT |
core_tl_o.d_source[5:0] | Yes | Yes | *T18,*T68,*T154 | Yes | T18,T68,T154 | OUTPUT |
core_tl_o.d_source[7:6] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
core_tl_o.d_size[1:0] | Yes | Yes | T73,T74,T75 | Yes | T73,T74,T75 | OUTPUT |
core_tl_o.d_param[2:0] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
core_tl_o.d_opcode[0] | Yes | Yes | *T40,*T109,*T18 | Yes | T40,T109,T18 | OUTPUT |
core_tl_o.d_opcode[2:1] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
core_tl_o.d_valid | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT |
prim_tl_i.d_ready | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
prim_tl_i.a_user.data_intg[6:0] | Yes | Yes | T57,T73,T74 | Yes | T57,T73,T74 | INPUT |
prim_tl_i.a_user.cmd_intg[6:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
prim_tl_i.a_user.instr_type[3:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
prim_tl_i.a_user.rsvd[4:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_data[31:0] | Yes | Yes | T57,T73,T75 | Yes | T57,T73,T75 | INPUT |
prim_tl_i.a_mask[3:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
prim_tl_i.a_address[4:0] | Yes | Yes | *T73,*T74,*T75 | Yes | T73,T74,T75 | INPUT |
prim_tl_i.a_address[14:5] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_address[17:15] | Yes | Yes | *T57,*T73,*T74 | Yes | T57,T73,T74 | INPUT |
prim_tl_i.a_address[19:18] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_address[20] | Yes | Yes | *T4,*T6,*T15 | Yes | T4,T6,T15 | INPUT |
prim_tl_i.a_address[29:21] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_address[30] | Yes | Yes | *T4,*T6,*T15 | Yes | T4,T6,T15 | INPUT |
prim_tl_i.a_address[31] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_source[5:0] | Yes | Yes | *T18,*T68,*T76 | Yes | T18,T68,T76 | INPUT |
prim_tl_i.a_source[7:6] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_size[1:0] | Yes | Yes | T73,T74,T75 | Yes | T73,T74,T75 | INPUT |
prim_tl_i.a_param[2:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_opcode[2:0] | Yes | Yes | T76,T72,T77 | Yes | T76,T72,T77 | INPUT |
prim_tl_i.a_valid | Yes | Yes | T57,T73,T74 | Yes | T57,T73,T74 | INPUT |
prim_tl_o.a_ready | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT |
prim_tl_o.d_error | Yes | Yes | T4,T6,T15 | Yes | T6,T17,T16 | OUTPUT |
prim_tl_o.d_user.data_intg[6:0] | Yes | Yes | T57,T73,T74 | Yes | T57,T73,T74 | OUTPUT |
prim_tl_o.d_user.rsp_intg[6:0] | Yes | Yes | T57,T73,T74 | Yes | T57,T73,T74 | OUTPUT |
prim_tl_o.d_data[31:0] | Yes | Yes | T4,T6,T15 | Yes | T6,T17,T16 | OUTPUT |
prim_tl_o.d_sink | Yes | Yes | T73,T74,T75 | Yes | T73,T74,T75 | OUTPUT |
prim_tl_o.d_source[5:0] | Yes | Yes | *T57,T73,*T74 | Yes | T57,T73,T74 | OUTPUT |
prim_tl_o.d_source[7:6] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
prim_tl_o.d_size[1:0] | Yes | Yes | T73,T74,T75 | Yes | T73,T74,T75 | OUTPUT |
prim_tl_o.d_param[2:0] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
prim_tl_o.d_opcode[0] | Yes | Yes | *T4,*T6,*T15 | Yes | T6,T17,T16 | OUTPUT |
prim_tl_o.d_opcode[2:1] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
prim_tl_o.d_valid | Yes | Yes | T57,T73,T74 | Yes | T57,T73,T74 | OUTPUT |
intr_otp_operation_done_o | Yes | Yes | T166,T167,T168 | Yes | T166,T167,T168 | OUTPUT |
intr_otp_error_o | Yes | Yes | T166,T167,T168 | Yes | T166,T167,T168 | OUTPUT |
alert_rx_i[0].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
alert_rx_i[0].ack_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | INPUT |
alert_rx_i[0].ping_n | Yes | Yes | T78,T79,T169 | Yes | T78,T79,T169 | INPUT |
alert_rx_i[0].ping_p | Yes | Yes | T78,T79,T169 | Yes | T78,T79,T169 | INPUT |
alert_rx_i[1].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
alert_rx_i[1].ack_p | Yes | Yes | T5,T39,T78 | Yes | T5,T39,T78 | INPUT |
alert_rx_i[1].ping_n | Yes | Yes | T78,T79,T169 | Yes | T78,T79,T169 | INPUT |
alert_rx_i[1].ping_p | Yes | Yes | T78,T79,T169 | Yes | T78,T79,T169 | INPUT |
alert_rx_i[2].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
alert_rx_i[2].ack_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | INPUT |
alert_rx_i[2].ping_n | Yes | Yes | T78,T79,T81 | Yes | T78,T79,T81 | INPUT |
alert_rx_i[2].ping_p | Yes | Yes | T78,T79,T81 | Yes | T78,T79,T81 | INPUT |
alert_rx_i[3].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
alert_rx_i[3].ack_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | INPUT |
alert_rx_i[3].ping_n | Yes | Yes | T78,T79,T81 | Yes | T78,T79,T81 | INPUT |
alert_rx_i[3].ping_p | Yes | Yes | T78,T79,T81 | Yes | T78,T79,T81 | INPUT |
alert_rx_i[4].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
alert_rx_i[4].ack_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | INPUT |
alert_rx_i[4].ping_n | Yes | Yes | T78,T79,T81 | Yes | T78,T79,T81 | INPUT |
alert_rx_i[4].ping_p | Yes | Yes | T78,T79,T81 | Yes | T78,T79,T81 | INPUT |
alert_tx_o[0].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
alert_tx_o[0].alert_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | OUTPUT |
alert_tx_o[1].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
alert_tx_o[1].alert_p | Yes | Yes | T5,T39,T78 | Yes | T5,T39,T78 | OUTPUT |
alert_tx_o[2].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
alert_tx_o[2].alert_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | OUTPUT |
alert_tx_o[3].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
alert_tx_o[3].alert_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | OUTPUT |
alert_tx_o[4].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
alert_tx_o[4].alert_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | OUTPUT |
obs_ctrl_i.obmen[3:0] | No | No | No | INPUT | ||
obs_ctrl_i.obmsl[3:0] | No | No | No | INPUT | ||
obs_ctrl_i.obgsl[3:0] | No | No | No | INPUT | ||
otp_obs_o[7:0] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
otp_ast_pwr_seq_o.pwr_seq[1:0] | No | No | No | OUTPUT | ||
otp_ast_pwr_seq_h_i.pwr_seq_h[0] | No | No | No | INPUT | ||
otp_ast_pwr_seq_h_i.pwr_seq_h[1] | Yes | Yes | T4,T5,T6 | Yes | T6,T17,T16 | INPUT |
pwr_otp_i.otp_init | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
pwr_otp_o.otp_idle | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | OUTPUT |
pwr_otp_o.otp_done | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | OUTPUT |
lc_otp_vendor_test_i.ctrl[10:0] | No | No | Yes | T170,T171,T172 | INPUT | |
lc_otp_vendor_test_i.ctrl[11] | No | No | No | INPUT | ||
lc_otp_vendor_test_i.ctrl[15:12] | No | No | Yes | T171,T170 | INPUT | |
lc_otp_vendor_test_i.ctrl[16] | No | No | No | INPUT | ||
lc_otp_vendor_test_i.ctrl[19:17] | No | No | Yes | T170,T171,T172 | INPUT | |
lc_otp_vendor_test_i.ctrl[20] | No | No | No | INPUT | ||
lc_otp_vendor_test_i.ctrl[22:21] | No | No | Yes | T170,T171 | INPUT | |
lc_otp_vendor_test_i.ctrl[24:23] | No | No | No | INPUT | ||
lc_otp_vendor_test_i.ctrl[25] | No | No | Yes | T170,T171 | INPUT | |
lc_otp_vendor_test_i.ctrl[26] | No | No | No | INPUT | ||
lc_otp_vendor_test_i.ctrl[31:27] | No | No | Yes | T170,T172,T171 | INPUT | |
lc_otp_vendor_test_o.status[31:0] | No | No | No | OUTPUT | ||
lc_otp_program_i.count[9:0] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[10] | No | No | No | INPUT | ||
lc_otp_program_i.count[15:11] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[17:16] | No | No | No | INPUT | ||
lc_otp_program_i.count[25:18] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[26] | No | No | No | INPUT | ||
lc_otp_program_i.count[31:27] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[32] | No | No | No | INPUT | ||
lc_otp_program_i.count[34:33] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[35] | No | No | No | INPUT | ||
lc_otp_program_i.count[37:36] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[38] | No | No | No | INPUT | ||
lc_otp_program_i.count[49:39] | Yes | Yes | *T174,*T62,*T53 | Yes | T174,T62,T50 | INPUT |
lc_otp_program_i.count[50] | No | No | No | INPUT | ||
lc_otp_program_i.count[53:51] | Yes | Yes | T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT |
lc_otp_program_i.count[55:54] | No | No | No | INPUT | ||
lc_otp_program_i.count[66:56] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[67] | No | No | No | INPUT | ||
lc_otp_program_i.count[74:68] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT |
lc_otp_program_i.count[75] | No | No | No | INPUT | ||
lc_otp_program_i.count[78:76] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[79] | No | No | No | INPUT | ||
lc_otp_program_i.count[86:80] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[87] | No | No | No | INPUT | ||
lc_otp_program_i.count[104:88] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT |
lc_otp_program_i.count[105] | No | No | No | INPUT | ||
lc_otp_program_i.count[110:106] | Yes | Yes | *T19,*T52,*T62 | Yes | T62,T50,T175 | INPUT |
lc_otp_program_i.count[111] | No | No | No | INPUT | ||
lc_otp_program_i.count[121:112] | Yes | Yes | *T19,*T52,T62 | Yes | T62,T50,T175 | INPUT |
lc_otp_program_i.count[122] | No | No | No | INPUT | ||
lc_otp_program_i.count[123] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[124] | No | No | No | INPUT | ||
lc_otp_program_i.count[128:125] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[129] | No | No | No | INPUT | ||
lc_otp_program_i.count[147:130] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[148] | No | No | No | INPUT | ||
lc_otp_program_i.count[156:149] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[157] | No | No | No | INPUT | ||
lc_otp_program_i.count[163:158] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[164] | No | No | No | INPUT | ||
lc_otp_program_i.count[169:165] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT |
lc_otp_program_i.count[170] | No | No | No | INPUT | ||
lc_otp_program_i.count[181:171] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[182] | No | No | No | INPUT | ||
lc_otp_program_i.count[184:183] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT |
lc_otp_program_i.count[186:185] | No | No | No | INPUT | ||
lc_otp_program_i.count[199:187] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT |
lc_otp_program_i.count[200] | No | No | No | INPUT | ||
lc_otp_program_i.count[207:201] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[208] | No | No | No | INPUT | ||
lc_otp_program_i.count[216:209] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT |
lc_otp_program_i.count[217] | No | No | No | INPUT | ||
lc_otp_program_i.count[237:218] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT |
lc_otp_program_i.count[238] | No | No | No | INPUT | ||
lc_otp_program_i.count[248:239] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[250:249] | No | No | No | INPUT | ||
lc_otp_program_i.count[260:251] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[261] | No | No | No | INPUT | ||
lc_otp_program_i.count[268:262] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT |
lc_otp_program_i.count[269] | No | No | No | INPUT | ||
lc_otp_program_i.count[271:270] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | INPUT |
lc_otp_program_i.count[272] | No | No | No | INPUT | ||
lc_otp_program_i.count[275:273] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT |
lc_otp_program_i.count[276] | No | No | No | INPUT | ||
lc_otp_program_i.count[277] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT |
lc_otp_program_i.count[278] | No | No | No | INPUT | ||
lc_otp_program_i.count[299:279] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[300] | No | No | No | INPUT | ||
lc_otp_program_i.count[306:301] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT |
lc_otp_program_i.count[308:307] | No | No | No | INPUT | ||
lc_otp_program_i.count[311:309] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT |
lc_otp_program_i.count[312] | No | No | No | INPUT | ||
lc_otp_program_i.count[320:313] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT |
lc_otp_program_i.count[321] | No | No | No | INPUT | ||
lc_otp_program_i.count[330:322] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT |
lc_otp_program_i.count[331] | No | No | No | INPUT | ||
lc_otp_program_i.count[332] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[333] | No | No | No | INPUT | ||
lc_otp_program_i.count[348:334] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT |
lc_otp_program_i.count[349] | No | No | No | INPUT | ||
lc_otp_program_i.count[357:350] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[358] | No | No | No | INPUT | ||
lc_otp_program_i.count[362:359] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.count[363] | No | No | No | INPUT | ||
lc_otp_program_i.count[369:364] | Yes | Yes | *T174,*T4,*T5 | Yes | T174,T5,T6 | INPUT |
lc_otp_program_i.count[370] | No | No | No | INPUT | ||
lc_otp_program_i.count[383:371] | Yes | Yes | T174,T4,T5 | Yes | T174,T5,T6 | INPUT |
lc_otp_program_i.state[2:0] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[3] | No | No | No | INPUT | ||
lc_otp_program_i.state[7:4] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[9:8] | No | No | No | INPUT | ||
lc_otp_program_i.state[11:10] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[12] | No | No | No | INPUT | ||
lc_otp_program_i.state[14:13] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[15] | No | No | No | INPUT | ||
lc_otp_program_i.state[17:16] | Yes | Yes | T62,T53,T113 | Yes | T62,T50,T176 | INPUT |
lc_otp_program_i.state[18] | No | No | No | INPUT | ||
lc_otp_program_i.state[24:19] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[26:25] | No | No | No | INPUT | ||
lc_otp_program_i.state[37:27] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[38] | No | No | No | INPUT | ||
lc_otp_program_i.state[58:39] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | INPUT |
lc_otp_program_i.state[59] | No | No | No | INPUT | ||
lc_otp_program_i.state[63:60] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[64] | No | No | No | INPUT | ||
lc_otp_program_i.state[71:65] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | INPUT |
lc_otp_program_i.state[72] | No | No | No | INPUT | ||
lc_otp_program_i.state[93:73] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[94] | No | No | No | INPUT | ||
lc_otp_program_i.state[101:95] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT |
lc_otp_program_i.state[102] | No | No | No | INPUT | ||
lc_otp_program_i.state[103] | Yes | Yes | *T174 | Yes | T174 | INPUT |
lc_otp_program_i.state[104] | No | No | No | INPUT | ||
lc_otp_program_i.state[124:105] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | INPUT |
lc_otp_program_i.state[125] | No | No | No | INPUT | ||
lc_otp_program_i.state[129:126] | Yes | Yes | *T174,*T5,*T62 | Yes | T174,T5,T62 | INPUT |
lc_otp_program_i.state[130] | No | No | No | INPUT | ||
lc_otp_program_i.state[133:131] | Yes | Yes | *T5,T62,*T53 | Yes | T5,T62,T50 | INPUT |
lc_otp_program_i.state[134] | No | No | No | INPUT | ||
lc_otp_program_i.state[138:135] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | INPUT |
lc_otp_program_i.state[139] | No | No | No | INPUT | ||
lc_otp_program_i.state[141:140] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[142] | No | No | No | INPUT | ||
lc_otp_program_i.state[157:143] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | INPUT |
lc_otp_program_i.state[158] | No | No | No | INPUT | ||
lc_otp_program_i.state[172:159] | Yes | Yes | *T5,*T18,*T62 | Yes | T5,T18,T62 | INPUT |
lc_otp_program_i.state[173] | No | No | No | INPUT | ||
lc_otp_program_i.state[177:174] | Yes | Yes | *T174,*T5,*T18 | Yes | T174,T5,T18 | INPUT |
lc_otp_program_i.state[179:178] | No | No | No | INPUT | ||
lc_otp_program_i.state[182:180] | Yes | Yes | *T5,*T18,T62 | Yes | T5,T18,T62 | INPUT |
lc_otp_program_i.state[183] | No | No | No | INPUT | ||
lc_otp_program_i.state[196:184] | Yes | Yes | *T174,*T5,*T18 | Yes | T174,T5,T18 | INPUT |
lc_otp_program_i.state[197] | No | No | No | INPUT | ||
lc_otp_program_i.state[198] | Yes | Yes | *T5,*T18,*T62 | Yes | T5,T18,T62 | INPUT |
lc_otp_program_i.state[199] | No | No | No | INPUT | ||
lc_otp_program_i.state[213:200] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[214] | No | No | No | INPUT | ||
lc_otp_program_i.state[218:215] | Yes | Yes | *T5,*T18,T62 | Yes | T5,T18,T62 | INPUT |
lc_otp_program_i.state[219] | No | No | No | INPUT | ||
lc_otp_program_i.state[225:220] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[226] | No | No | No | INPUT | ||
lc_otp_program_i.state[234:227] | Yes | Yes | *T5,*T18,*T62 | Yes | T5,T18,T62 | INPUT |
lc_otp_program_i.state[235] | No | No | No | INPUT | ||
lc_otp_program_i.state[240:236] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[241] | No | No | No | INPUT | ||
lc_otp_program_i.state[249:242] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT |
lc_otp_program_i.state[250] | No | No | No | INPUT | ||
lc_otp_program_i.state[264:251] | Yes | Yes | T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[266:265] | No | No | No | INPUT | ||
lc_otp_program_i.state[270:267] | Yes | Yes | *T174,*T5,*T56 | Yes | T174,T5,T18 | INPUT |
lc_otp_program_i.state[271] | No | No | No | INPUT | ||
lc_otp_program_i.state[280:272] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT |
lc_otp_program_i.state[281] | No | No | No | INPUT | ||
lc_otp_program_i.state[286:282] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[287] | No | No | No | INPUT | ||
lc_otp_program_i.state[305:288] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.state[306] | No | No | No | INPUT | ||
lc_otp_program_i.state[319:307] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT |
lc_otp_program_i.req | Yes | Yes | T5,T18,T62 | Yes | T5,T18,T62 | INPUT |
lc_otp_program_o.ack | Yes | Yes | T5,T18,T62 | Yes | T5,T18,T62 | OUTPUT |
lc_otp_program_o.err | Yes | Yes | T177,T178,T179 | Yes | T177,T178,T179 | OUTPUT |
lc_creator_seed_sw_rw_en_i[3:0] | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | INPUT |
lc_owner_seed_sw_rw_en_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
lc_seed_hw_rd_en_i[3:0] | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | INPUT |
lc_dft_en_i[3:0] | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | INPUT |
lc_escalate_en_i[3:0] | Yes | Yes | T39,T63,T55 | Yes | T5,T39,T63 | INPUT |
lc_check_byp_en_i[3:0] | Yes | Yes | T5,T18,T62 | Yes | T5,T18,T62 | INPUT |
otp_lc_data_o.rma_token[127:0] | Yes | Yes | T63,T146,T147 | Yes | T4,T82,T22 | OUTPUT |
otp_lc_data_o.rma_token_valid[3:0] | Yes | Yes | T49,T176,T180 | Yes | T40,T109,T103 | OUTPUT |
otp_lc_data_o.test_exit_token[127:0] | Yes | Yes | T5,T6,T17 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.test_unlock_token[127:0] | Yes | Yes | T6,T39,T40 | Yes | T4,T6,T15 | OUTPUT |
otp_lc_data_o.test_tokens_valid[3:0] | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.secrets_valid[3:0] | Yes | Yes | T49,T176,T180 | Yes | T40,T109,T103 | OUTPUT |
otp_lc_data_o.count[9:0] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.count[10] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[15:11] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[17:16] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[25:18] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[26] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[31:27] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.count[32] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[34:33] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[35] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[37:36] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.count[38] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[49:39] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[50] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[53:51] | Yes | Yes | *T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[55:54] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[66:56] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[67] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[74:68] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[75] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[78:76] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[79] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[86:80] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.count[87] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[104:88] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[105] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[110:106] | Yes | Yes | *T19,*T52,*T62 | Yes | T62,T50,T175 | OUTPUT |
otp_lc_data_o.count[111] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[121:112] | Yes | Yes | *T19,*T52,*T62 | Yes | T62,T50,T175 | OUTPUT |
otp_lc_data_o.count[122] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[123] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.count[124] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[128:125] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.count[129] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[147:130] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.count[148] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[156:149] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[157] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[163:158] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[164] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[169:165] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[170] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[181:171] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[182] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[184:183] | Yes | Yes | *T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[186:185] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[199:187] | Yes | Yes | *T5,*T62,*T114 | Yes | T5,T62,T114 | OUTPUT |
otp_lc_data_o.count[200] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[207:201] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.count[208] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[216:209] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[217] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[237:218] | Yes | Yes | *T5,*T62,*T114 | Yes | T5,T62,T114 | OUTPUT |
otp_lc_data_o.count[238] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[248:239] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.count[250:249] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[260:251] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[261] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[268:262] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[269] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[271:270] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[272] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[275:273] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[276] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[277] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[278] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[299:279] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[300] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[306:301] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[308:307] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[311:309] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[312] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[320:313] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[321] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[330:322] | Yes | Yes | T5,*T114,*T182 | Yes | T5,T114,T177 | OUTPUT |
otp_lc_data_o.count[331] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[332] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[333] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[348:334] | Yes | Yes | *T5,*T114,*T182 | Yes | T5,T114,T177 | OUTPUT |
otp_lc_data_o.count[349] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[357:350] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[358] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[362:359] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.count[363] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[369:364] | Yes | Yes | *T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.count[370] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[383:371] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.state[2:0] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.state[3] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[7:4] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[9:8] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[11:10] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[12] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[14:13] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[15] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[17:16] | Yes | Yes | T62,T53,T113 | Yes | T62,T50,T176 | OUTPUT |
otp_lc_data_o.state[18] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[24:19] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[26:25] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[37:27] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.state[38] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[58:39] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | OUTPUT |
otp_lc_data_o.state[59] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[63:60] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.state[64] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[71:65] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[72] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[93:73] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[94] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[101:95] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.state[102] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[103] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.state[104] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[124:105] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | OUTPUT |
otp_lc_data_o.state[125] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[129:126] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.state[130] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[133:131] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[134] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[138:135] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | OUTPUT |
otp_lc_data_o.state[139] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[141:140] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.state[142] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[157:143] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[158] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[172:159] | Yes | Yes | T5,*T18,*T62 | Yes | T5,T18,T62 | OUTPUT |
otp_lc_data_o.state[173] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[177:174] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.state[179:178] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[182:180] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[183] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[196:184] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.state[197] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[198] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[199] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[213:200] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.state[214] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[218:215] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[219] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[225:220] | Yes | Yes | T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[226] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[234:227] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[235] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[240:236] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.state[241] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[249:242] | Yes | Yes | *T4,T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.state[250] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[264:251] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.state[266:265] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[270:267] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.state[271] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[280:272] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.state[281] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[286:282] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT |
otp_lc_data_o.state[287] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[305:288] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[306] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[319:307] | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.error | Yes | Yes | T39,T63,T55 | Yes | T5,T39,T63 | OUTPUT |
otp_lc_data_o.valid | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | OUTPUT |
otp_keymgr_key_o.owner_seed_valid | No | No | No | OUTPUT | ||
otp_keymgr_key_o.owner_seed[255:0] | No | No | No | OUTPUT | ||
otp_keymgr_key_o.creator_seed_valid | No | No | No | OUTPUT | ||
otp_keymgr_key_o.creator_seed[255:0] | No | No | No | OUTPUT | ||
otp_keymgr_key_o.creator_root_key_share1_valid | Yes | Yes | T49,T176,T180 | Yes | T40,T109,T103 | OUTPUT |
otp_keymgr_key_o.creator_root_key_share1[255:0] | Yes | Yes | T16,T39,T146 | Yes | T15,T82,T16 | OUTPUT |
otp_keymgr_key_o.creator_root_key_share0_valid | Yes | Yes | T49,T176,T180 | Yes | T40,T109,T103 | OUTPUT |
otp_keymgr_key_o.creator_root_key_share0[255:0] | Yes | Yes | T6,T147,T55 | Yes | T4,T6,T15 | OUTPUT |
flash_otp_key_i.addr_req | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
flash_otp_key_i.data_req | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
flash_otp_key_o.seed_valid | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT |
flash_otp_key_o.rand_key[127:0] | Yes | Yes | T6,T15,T17 | Yes | T4,T6,T15 | OUTPUT |
flash_otp_key_o.key[127:0] | Yes | Yes | T15,T82,T22 | Yes | T82,T17,T16 | OUTPUT |
flash_otp_key_o.addr_ack | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT |
flash_otp_key_o.data_ack | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT |
sram_otp_key_i[0].req | Yes | Yes | T52,T53,T54 | Yes | T52,T53,T54 | INPUT |
sram_otp_key_i[1].req | Yes | Yes | T183,T112,T184 | Yes | T183,T112,T184 | INPUT |
sram_otp_key_i[2].req | Yes | Yes | T185,T186,T187 | Yes | T185,T186,T187 | INPUT |
sram_otp_key_i[3].req | No | No | No | INPUT | ||
sram_otp_key_o[0].seed_valid | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT |
sram_otp_key_o[0].nonce[127:0] | Yes | Yes | T6,T15,T17 | Yes | T4,T6,T15 | OUTPUT |
sram_otp_key_o[0].key[127:0] | Yes | Yes | T15,T82,T22 | Yes | T82,T17,T16 | OUTPUT |
sram_otp_key_o[0].ack | Yes | Yes | T52,T53,T54 | Yes | T52,T53,T54 | OUTPUT |
sram_otp_key_o[1].seed_valid | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT |
sram_otp_key_o[1].nonce[127:0] | Yes | Yes | T6,T15,T17 | Yes | T4,T6,T15 | OUTPUT |
sram_otp_key_o[1].key[127:0] | Yes | Yes | T15,T82,T22 | Yes | T82,T17,T16 | OUTPUT |
sram_otp_key_o[1].ack | Yes | Yes | T183,T112,T184 | Yes | T183,T112,T184 | OUTPUT |
sram_otp_key_o[2].seed_valid | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT |
sram_otp_key_o[2].nonce[127:0] | Yes | Yes | T6,T15,T17 | Yes | T4,T6,T15 | OUTPUT |
sram_otp_key_o[2].key[127:0] | Yes | Yes | T15,T82,T22 | Yes | T82,T17,T16 | OUTPUT |
sram_otp_key_o[2].ack | Yes | Yes | T186,T187,T188 | Yes | T186,T187,T188 | OUTPUT |
sram_otp_key_o[3].seed_valid | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT |
sram_otp_key_o[3].nonce[127:0] | Yes | Yes | T6,T15,T17 | Yes | T4,T6,T15 | OUTPUT |
sram_otp_key_o[3].key[127:0] | Yes | Yes | T15,T82,T22 | Yes | T82,T17,T16 | OUTPUT |
sram_otp_key_o[3].ack | No | No | No | OUTPUT | ||
otbn_otp_key_i.req | Yes | Yes | T82,T164,T52 | Yes | T82,T164,T52 | INPUT |
otbn_otp_key_o.seed_valid | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT |
otbn_otp_key_o.nonce[63:0] | Yes | Yes | T6,T15,T17 | Yes | T4,T6,T15 | OUTPUT |
otbn_otp_key_o.key[127:0] | Yes | Yes | T15,T82,T22 | Yes | T82,T17,T16 | OUTPUT |
otbn_otp_key_o.ack | Yes | Yes | T82,T164,T52 | Yes | T82,T164,T52 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.device_id[255:0] | Yes | Yes | T4,T15,T82 | Yes | T17,T16,T39 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[2:0] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[3] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[11:4] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[12] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[90:13] | Yes | Yes | *T185,*T189,*T116 | Yes | T185,T189,T116 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[91] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[167:92] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[168] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[193:169] | Yes | Yes | *T185,*T189,*T116 | Yes | T185,T189,T116 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[194] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[198:195] | Yes | Yes | *T185,*T189,*T116 | Yes | T185,T189,T116 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[199] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[239:200] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[240] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[255:241] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0] | Yes | Yes | T6,T17,T63 | Yes | T4,T6,T15 | OUTPUT |
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT |
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT |
otp_broadcast_o.hw_cfg1_data.dis_rv_dm_late_debug[7:0] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT |
otp_broadcast_o.hw_cfg1_data.unallocated[39:0] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0] | Yes | Yes | T52,T62,T53 | Yes | T62,T185,T49 | OUTPUT |
otp_broadcast_o.valid[3:0] | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | OUTPUT |
otp_ext_voltage_h_io | No | No | Yes | T19,T20,T21 | INOUT | |
scan_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
scan_rst_ni | Unreachable | Unreachable | Unreachable | INPUT | ||
scanmode_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
cio_test_o[7:0] | No | No | No | OUTPUT | ||
cio_test_en_o[7:0] | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 160 | 142 | 88.75 |
Total Bits | 10986 | 9387 | 85.45 |
Total Bits 0->1 | 5493 | 4707 | 85.69 |
Total Bits 1->0 | 5493 | 4680 | 85.20 |
Ports | 160 | 142 | 88.75 |
Port Bits | 10986 | 9387 | 85.45 |
Port Bits 0->1 | 5493 | 4707 | 85.69 |
Port Bits 1->0 | 5493 | 4680 | 85.20 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction | Exclude Annotation |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
rst_ni | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | INPUT | |
clk_edn_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
rst_edn_ni | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | INPUT | |
edn_o.edn_req | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT | |
edn_i.edn_bus[31:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
edn_i.edn_fips | No | No | Yes | T164,T110,T165 | INPUT | ||
edn_i.edn_ack | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
core_tl_i.d_ready | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
core_tl_i.a_user.data_intg[6:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
core_tl_i.a_user.cmd_intg[6:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
core_tl_i.a_user.instr_type[3:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
core_tl_i.a_user.rsvd[4:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_data[31:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
core_tl_i.a_mask[3:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
core_tl_i.a_address[11:0] | Yes | Yes | *T73,*T74,*T75 | Yes | T73,T74,T75 | INPUT | |
core_tl_i.a_address[15:12] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_address[17:16] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
core_tl_i.a_address[19:18] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_address[20] | Yes | Yes | *T4,*T6,*T15 | Yes | T4,T6,T15 | INPUT | |
core_tl_i.a_address[29:21] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_address[30] | Yes | Yes | *T4,*T6,*T15 | Yes | T4,T6,T15 | INPUT | |
core_tl_i.a_address[31] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_source[5:0] | Yes | Yes | *T18,*T68,*T76 | Yes | T18,T68,T76 | INPUT | |
core_tl_i.a_source[7:6] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_size[1:0] | Yes | Yes | T73,T74,T75 | Yes | T73,T74,T75 | INPUT | |
core_tl_i.a_param[2:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_opcode[2:0] | Yes | Yes | T76,T72,T77 | Yes | T76,T72,T77 | INPUT | |
core_tl_i.a_valid | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
core_tl_o.a_ready | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT | |
core_tl_o.d_error | Yes | Yes | T73,T74,T117 | Yes | T73,T74,T75 | OUTPUT | |
core_tl_o.d_user.data_intg[6:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT | |
core_tl_o.d_user.rsp_intg[6:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT | |
core_tl_o.d_data[31:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT | |
core_tl_o.d_sink | Yes | Yes | T73,T75,T117 | Yes | T73,T74,T75 | OUTPUT | |
core_tl_o.d_source[5:0] | Yes | Yes | *T18,*T68,*T154 | Yes | T18,T68,T154 | OUTPUT | |
core_tl_o.d_source[7:6] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
core_tl_o.d_size[1:0] | Yes | Yes | T73,T74,T75 | Yes | T73,T74,T75 | OUTPUT | |
core_tl_o.d_param[2:0] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
core_tl_o.d_opcode[0] | Yes | Yes | *T40,*T109,*T18 | Yes | T40,T109,T18 | OUTPUT | |
core_tl_o.d_opcode[2:1] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
core_tl_o.d_valid | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT | |
prim_tl_i.d_ready | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
prim_tl_i.a_user.data_intg[6:0] | Yes | Yes | T57,T73,T74 | Yes | T57,T73,T74 | INPUT | |
prim_tl_i.a_user.cmd_intg[6:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
prim_tl_i.a_user.instr_type[3:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
prim_tl_i.a_user.rsvd[4:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_data[31:0] | Yes | Yes | T57,T73,T75 | Yes | T57,T73,T75 | INPUT | |
prim_tl_i.a_mask[3:0] | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
prim_tl_i.a_address[4:0] | Yes | Yes | *T73,*T74,*T75 | Yes | T73,T74,T75 | INPUT | |
prim_tl_i.a_address[14:5] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_address[17:15] | Yes | Yes | *T57,*T73,*T74 | Yes | T57,T73,T74 | INPUT | |
prim_tl_i.a_address[19:18] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_address[20] | Yes | Yes | *T4,*T6,*T15 | Yes | T4,T6,T15 | INPUT | |
prim_tl_i.a_address[29:21] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_address[30] | Yes | Yes | *T4,*T6,*T15 | Yes | T4,T6,T15 | INPUT | |
prim_tl_i.a_address[31] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_source[5:0] | Yes | Yes | *T18,*T68,*T76 | Yes | T18,T68,T76 | INPUT | |
prim_tl_i.a_source[7:6] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_size[1:0] | Yes | Yes | T73,T74,T75 | Yes | T73,T74,T75 | INPUT | |
prim_tl_i.a_param[2:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_opcode[2:0] | Yes | Yes | T76,T72,T77 | Yes | T76,T72,T77 | INPUT | |
prim_tl_i.a_valid | Yes | Yes | T57,T73,T74 | Yes | T57,T73,T74 | INPUT | |
prim_tl_o.a_ready | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT | |
prim_tl_o.d_error | Yes | Yes | T4,T6,T15 | Yes | T6,T17,T16 | OUTPUT | |
prim_tl_o.d_user.data_intg[6:0] | Yes | Yes | T57,T73,T74 | Yes | T57,T73,T74 | OUTPUT | |
prim_tl_o.d_user.rsp_intg[6:0] | Yes | Yes | T57,T73,T74 | Yes | T57,T73,T74 | OUTPUT | |
prim_tl_o.d_data[31:0] | Yes | Yes | T4,T6,T15 | Yes | T6,T17,T16 | OUTPUT | |
prim_tl_o.d_sink | Yes | Yes | T73,T74,T75 | Yes | T73,T74,T75 | OUTPUT | |
prim_tl_o.d_source[5:0] | Yes | Yes | *T57,T73,*T74 | Yes | T57,T73,T74 | OUTPUT | |
prim_tl_o.d_source[7:6] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
prim_tl_o.d_size[1:0] | Yes | Yes | T73,T74,T75 | Yes | T73,T74,T75 | OUTPUT | |
prim_tl_o.d_param[2:0] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
prim_tl_o.d_opcode[0] | Yes | Yes | *T4,*T6,*T15 | Yes | T6,T17,T16 | OUTPUT | |
prim_tl_o.d_opcode[2:1] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
prim_tl_o.d_valid | Yes | Yes | T57,T73,T74 | Yes | T57,T73,T74 | OUTPUT | |
intr_otp_operation_done_o | Yes | Yes | T166,T167,T168 | Yes | T166,T167,T168 | OUTPUT | |
intr_otp_error_o | Yes | Yes | T166,T167,T168 | Yes | T166,T167,T168 | OUTPUT | |
alert_rx_i[0].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
alert_rx_i[0].ack_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | INPUT | |
alert_rx_i[0].ping_n | Yes | Yes | T78,T79,T169 | Yes | T78,T79,T169 | INPUT | |
alert_rx_i[0].ping_p | Yes | Yes | T78,T79,T169 | Yes | T78,T79,T169 | INPUT | |
alert_rx_i[1].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
alert_rx_i[1].ack_p | Yes | Yes | T5,T39,T78 | Yes | T5,T39,T78 | INPUT | |
alert_rx_i[1].ping_n | Yes | Yes | T78,T79,T169 | Yes | T78,T79,T169 | INPUT | |
alert_rx_i[1].ping_p | Yes | Yes | T78,T79,T169 | Yes | T78,T79,T169 | INPUT | |
alert_rx_i[2].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
alert_rx_i[2].ack_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | INPUT | |
alert_rx_i[2].ping_n | Yes | Yes | T78,T79,T81 | Yes | T78,T79,T81 | INPUT | |
alert_rx_i[2].ping_p | Yes | Yes | T78,T79,T81 | Yes | T78,T79,T81 | INPUT | |
alert_rx_i[3].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
alert_rx_i[3].ack_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | INPUT | |
alert_rx_i[3].ping_n | Yes | Yes | T78,T79,T81 | Yes | T78,T79,T81 | INPUT | |
alert_rx_i[3].ping_p | Yes | Yes | T78,T79,T81 | Yes | T78,T79,T81 | INPUT | |
alert_rx_i[4].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
alert_rx_i[4].ack_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | INPUT | |
alert_rx_i[4].ping_n | Yes | Yes | T78,T79,T81 | Yes | T78,T79,T81 | INPUT | |
alert_rx_i[4].ping_p | Yes | Yes | T78,T79,T81 | Yes | T78,T79,T81 | INPUT | |
alert_tx_o[0].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
alert_tx_o[0].alert_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | OUTPUT | |
alert_tx_o[1].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
alert_tx_o[1].alert_p | Yes | Yes | T5,T39,T78 | Yes | T5,T39,T78 | OUTPUT | |
alert_tx_o[2].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
alert_tx_o[2].alert_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | OUTPUT | |
alert_tx_o[3].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
alert_tx_o[3].alert_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | OUTPUT | |
alert_tx_o[4].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
alert_tx_o[4].alert_p | Yes | Yes | T78,T79,T58 | Yes | T78,T79,T58 | OUTPUT | |
obs_ctrl_i.obmen[3:0] | Excluded | Excluded | Excluded | INPUT | [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV. | ||
obs_ctrl_i.obmsl[3:0] | Excluded | Excluded | Excluded | INPUT | [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV. | ||
obs_ctrl_i.obgsl[3:0] | Excluded | Excluded | Excluded | INPUT | [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV. | ||
otp_obs_o[7:0] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
otp_ast_pwr_seq_o.pwr_seq[1:0] | No | No | No | OUTPUT | |||
otp_ast_pwr_seq_h_i.pwr_seq_h[0] | No | No | No | INPUT | |||
otp_ast_pwr_seq_h_i.pwr_seq_h[1] | Yes | Yes | T4,T5,T6 | Yes | T6,T17,T16 | INPUT | |
pwr_otp_i.otp_init | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
pwr_otp_o.otp_idle | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | OUTPUT | |
pwr_otp_o.otp_done | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | OUTPUT | |
lc_otp_vendor_test_i.ctrl[10:0] | No | No | Yes | T170,T171,T172 | INPUT | ||
lc_otp_vendor_test_i.ctrl[11] | No | No | No | INPUT | |||
lc_otp_vendor_test_i.ctrl[15:12] | No | No | Yes | T171,T170 | INPUT | ||
lc_otp_vendor_test_i.ctrl[16] | No | No | No | INPUT | |||
lc_otp_vendor_test_i.ctrl[19:17] | No | No | Yes | T170,T171,T172 | INPUT | ||
lc_otp_vendor_test_i.ctrl[20] | No | No | No | INPUT | |||
lc_otp_vendor_test_i.ctrl[22:21] | No | No | Yes | T170,T171 | INPUT | ||
lc_otp_vendor_test_i.ctrl[24:23] | No | No | No | INPUT | |||
lc_otp_vendor_test_i.ctrl[25] | No | No | Yes | T170,T171 | INPUT | ||
lc_otp_vendor_test_i.ctrl[26] | No | No | No | INPUT | |||
lc_otp_vendor_test_i.ctrl[31:27] | No | No | Yes | T170,T172,T171 | INPUT | ||
lc_otp_vendor_test_o.status[31:0] | No | No | No | OUTPUT | |||
lc_otp_program_i.count[9:0] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[10] | No | No | No | INPUT | |||
lc_otp_program_i.count[15:11] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[17:16] | No | No | No | INPUT | |||
lc_otp_program_i.count[25:18] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[26] | No | No | No | INPUT | |||
lc_otp_program_i.count[31:27] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[32] | No | No | No | INPUT | |||
lc_otp_program_i.count[34:33] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[35] | No | No | No | INPUT | |||
lc_otp_program_i.count[37:36] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[38] | No | No | No | INPUT | |||
lc_otp_program_i.count[49:39] | Yes | Yes | *T174,*T62,*T53 | Yes | T174,T62,T50 | INPUT | |
lc_otp_program_i.count[50] | No | No | No | INPUT | |||
lc_otp_program_i.count[53:51] | Yes | Yes | T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT | |
lc_otp_program_i.count[55:54] | No | No | No | INPUT | |||
lc_otp_program_i.count[66:56] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[67] | No | No | No | INPUT | |||
lc_otp_program_i.count[74:68] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT | |
lc_otp_program_i.count[75] | No | No | No | INPUT | |||
lc_otp_program_i.count[78:76] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[79] | No | No | No | INPUT | |||
lc_otp_program_i.count[86:80] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[87] | No | No | No | INPUT | |||
lc_otp_program_i.count[104:88] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT | |
lc_otp_program_i.count[105] | No | No | No | INPUT | |||
lc_otp_program_i.count[110:106] | Yes | Yes | *T19,*T52,*T62 | Yes | T62,T50,T175 | INPUT | |
lc_otp_program_i.count[111] | No | No | No | INPUT | |||
lc_otp_program_i.count[121:112] | Yes | Yes | *T19,*T52,T62 | Yes | T62,T50,T175 | INPUT | |
lc_otp_program_i.count[122] | No | No | No | INPUT | |||
lc_otp_program_i.count[123] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[124] | No | No | No | INPUT | |||
lc_otp_program_i.count[128:125] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[129] | No | No | No | INPUT | |||
lc_otp_program_i.count[147:130] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[148] | No | No | No | INPUT | |||
lc_otp_program_i.count[156:149] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[157] | No | No | No | INPUT | |||
lc_otp_program_i.count[163:158] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[164] | No | No | No | INPUT | |||
lc_otp_program_i.count[169:165] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT | |
lc_otp_program_i.count[170] | No | No | No | INPUT | |||
lc_otp_program_i.count[181:171] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[182] | No | No | No | INPUT | |||
lc_otp_program_i.count[184:183] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT | |
lc_otp_program_i.count[186:185] | No | No | No | INPUT | |||
lc_otp_program_i.count[199:187] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT | |
lc_otp_program_i.count[200] | No | No | No | INPUT | |||
lc_otp_program_i.count[207:201] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[208] | No | No | No | INPUT | |||
lc_otp_program_i.count[216:209] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT | |
lc_otp_program_i.count[217] | No | No | No | INPUT | |||
lc_otp_program_i.count[237:218] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT | |
lc_otp_program_i.count[238] | No | No | No | INPUT | |||
lc_otp_program_i.count[248:239] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[250:249] | No | No | No | INPUT | |||
lc_otp_program_i.count[260:251] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[261] | No | No | No | INPUT | |||
lc_otp_program_i.count[268:262] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT | |
lc_otp_program_i.count[269] | No | No | No | INPUT | |||
lc_otp_program_i.count[271:270] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | INPUT | |
lc_otp_program_i.count[272] | No | No | No | INPUT | |||
lc_otp_program_i.count[275:273] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT | |
lc_otp_program_i.count[276] | No | No | No | INPUT | |||
lc_otp_program_i.count[277] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT | |
lc_otp_program_i.count[278] | No | No | No | INPUT | |||
lc_otp_program_i.count[299:279] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[300] | No | No | No | INPUT | |||
lc_otp_program_i.count[306:301] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT | |
lc_otp_program_i.count[308:307] | No | No | No | INPUT | |||
lc_otp_program_i.count[311:309] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT | |
lc_otp_program_i.count[312] | No | No | No | INPUT | |||
lc_otp_program_i.count[320:313] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT | |
lc_otp_program_i.count[321] | No | No | No | INPUT | |||
lc_otp_program_i.count[330:322] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT | |
lc_otp_program_i.count[331] | No | No | No | INPUT | |||
lc_otp_program_i.count[332] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[333] | No | No | No | INPUT | |||
lc_otp_program_i.count[348:334] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT | |
lc_otp_program_i.count[349] | No | No | No | INPUT | |||
lc_otp_program_i.count[357:350] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[358] | No | No | No | INPUT | |||
lc_otp_program_i.count[362:359] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.count[363] | No | No | No | INPUT | |||
lc_otp_program_i.count[369:364] | Yes | Yes | *T174,*T4,*T5 | Yes | T174,T5,T6 | INPUT | |
lc_otp_program_i.count[370] | No | No | No | INPUT | |||
lc_otp_program_i.count[383:371] | Yes | Yes | T174,T4,T5 | Yes | T174,T5,T6 | INPUT | |
lc_otp_program_i.state[2:0] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[3] | No | No | No | INPUT | |||
lc_otp_program_i.state[7:4] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[9:8] | No | No | No | INPUT | |||
lc_otp_program_i.state[11:10] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[12] | No | No | No | INPUT | |||
lc_otp_program_i.state[14:13] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[15] | No | No | No | INPUT | |||
lc_otp_program_i.state[17:16] | Yes | Yes | T62,T53,T113 | Yes | T62,T50,T176 | INPUT | |
lc_otp_program_i.state[18] | No | No | No | INPUT | |||
lc_otp_program_i.state[24:19] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[26:25] | No | No | No | INPUT | |||
lc_otp_program_i.state[37:27] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[38] | No | No | No | INPUT | |||
lc_otp_program_i.state[58:39] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | INPUT | |
lc_otp_program_i.state[59] | No | No | No | INPUT | |||
lc_otp_program_i.state[63:60] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[64] | No | No | No | INPUT | |||
lc_otp_program_i.state[71:65] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | INPUT | |
lc_otp_program_i.state[72] | No | No | No | INPUT | |||
lc_otp_program_i.state[93:73] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[94] | No | No | No | INPUT | |||
lc_otp_program_i.state[101:95] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT | |
lc_otp_program_i.state[102] | No | No | No | INPUT | |||
lc_otp_program_i.state[103] | Yes | Yes | *T174 | Yes | T174 | INPUT | |
lc_otp_program_i.state[104] | No | No | No | INPUT | |||
lc_otp_program_i.state[124:105] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | INPUT | |
lc_otp_program_i.state[125] | No | No | No | INPUT | |||
lc_otp_program_i.state[129:126] | Yes | Yes | *T174,*T5,*T62 | Yes | T174,T5,T62 | INPUT | |
lc_otp_program_i.state[130] | No | No | No | INPUT | |||
lc_otp_program_i.state[133:131] | Yes | Yes | *T5,T62,*T53 | Yes | T5,T62,T50 | INPUT | |
lc_otp_program_i.state[134] | No | No | No | INPUT | |||
lc_otp_program_i.state[138:135] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | INPUT | |
lc_otp_program_i.state[139] | No | No | No | INPUT | |||
lc_otp_program_i.state[141:140] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[142] | No | No | No | INPUT | |||
lc_otp_program_i.state[157:143] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | INPUT | |
lc_otp_program_i.state[158] | No | No | No | INPUT | |||
lc_otp_program_i.state[172:159] | Yes | Yes | *T5,*T18,*T62 | Yes | T5,T18,T62 | INPUT | |
lc_otp_program_i.state[173] | No | No | No | INPUT | |||
lc_otp_program_i.state[177:174] | Yes | Yes | *T174,*T5,*T18 | Yes | T174,T5,T18 | INPUT | |
lc_otp_program_i.state[179:178] | No | No | No | INPUT | |||
lc_otp_program_i.state[182:180] | Yes | Yes | *T5,*T18,T62 | Yes | T5,T18,T62 | INPUT | |
lc_otp_program_i.state[183] | No | No | No | INPUT | |||
lc_otp_program_i.state[196:184] | Yes | Yes | *T174,*T5,*T18 | Yes | T174,T5,T18 | INPUT | |
lc_otp_program_i.state[197] | No | No | No | INPUT | |||
lc_otp_program_i.state[198] | Yes | Yes | *T5,*T18,*T62 | Yes | T5,T18,T62 | INPUT | |
lc_otp_program_i.state[199] | No | No | No | INPUT | |||
lc_otp_program_i.state[213:200] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[214] | No | No | No | INPUT | |||
lc_otp_program_i.state[218:215] | Yes | Yes | *T5,*T18,T62 | Yes | T5,T18,T62 | INPUT | |
lc_otp_program_i.state[219] | No | No | No | INPUT | |||
lc_otp_program_i.state[225:220] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[226] | No | No | No | INPUT | |||
lc_otp_program_i.state[234:227] | Yes | Yes | *T5,*T18,*T62 | Yes | T5,T18,T62 | INPUT | |
lc_otp_program_i.state[235] | No | No | No | INPUT | |||
lc_otp_program_i.state[240:236] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[241] | No | No | No | INPUT | |||
lc_otp_program_i.state[249:242] | Yes | Yes | *T174,*T62,*T113 | Yes | T174,T62,T113 | INPUT | |
lc_otp_program_i.state[250] | No | No | No | INPUT | |||
lc_otp_program_i.state[264:251] | Yes | Yes | T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[266:265] | No | No | No | INPUT | |||
lc_otp_program_i.state[270:267] | Yes | Yes | *T174,*T5,*T56 | Yes | T174,T5,T18 | INPUT | |
lc_otp_program_i.state[271] | No | No | No | INPUT | |||
lc_otp_program_i.state[280:272] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | INPUT | |
lc_otp_program_i.state[281] | No | No | No | INPUT | |||
lc_otp_program_i.state[286:282] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[287] | No | No | No | INPUT | |||
lc_otp_program_i.state[305:288] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.state[306] | No | No | No | INPUT | |||
lc_otp_program_i.state[319:307] | Yes | Yes | T62,T113,T173 | Yes | T62,T113,T173 | INPUT | |
lc_otp_program_i.req | Yes | Yes | T5,T18,T62 | Yes | T5,T18,T62 | INPUT | |
lc_otp_program_o.ack | Yes | Yes | T5,T18,T62 | Yes | T5,T18,T62 | OUTPUT | |
lc_otp_program_o.err | Yes | Yes | T177,T178,T179 | Yes | T177,T178,T179 | OUTPUT | |
lc_creator_seed_sw_rw_en_i[3:0] | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | INPUT | |
lc_owner_seed_sw_rw_en_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
lc_seed_hw_rd_en_i[3:0] | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | INPUT | |
lc_dft_en_i[3:0] | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | INPUT | |
lc_escalate_en_i[3:0] | Yes | Yes | T39,T63,T55 | Yes | T5,T39,T63 | INPUT | |
lc_check_byp_en_i[3:0] | Yes | Yes | T5,T18,T62 | Yes | T5,T18,T62 | INPUT | |
otp_lc_data_o.rma_token[127:0] | Yes | Yes | T63,T146,T147 | Yes | T4,T82,T22 | OUTPUT | |
otp_lc_data_o.rma_token_valid[3:0] | Yes | Yes | T49,T176,T180 | Yes | T40,T109,T103 | OUTPUT | |
otp_lc_data_o.test_exit_token[127:0] | Yes | Yes | T5,T6,T17 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.test_unlock_token[127:0] | Yes | Yes | T6,T39,T40 | Yes | T4,T6,T15 | OUTPUT | |
otp_lc_data_o.test_tokens_valid[3:0] | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.secrets_valid[3:0] | Yes | Yes | T49,T176,T180 | Yes | T40,T109,T103 | OUTPUT | |
otp_lc_data_o.count[9:0] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.count[10] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[15:11] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[17:16] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[25:18] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[26] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[31:27] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.count[32] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[34:33] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[35] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[37:36] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.count[38] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[49:39] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[50] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[53:51] | Yes | Yes | *T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[55:54] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[66:56] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[67] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[74:68] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[75] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[78:76] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[79] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[86:80] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.count[87] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[104:88] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[105] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[110:106] | Yes | Yes | *T19,*T52,*T62 | Yes | T62,T50,T175 | OUTPUT | |
otp_lc_data_o.count[111] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[121:112] | Yes | Yes | *T19,*T52,*T62 | Yes | T62,T50,T175 | OUTPUT | |
otp_lc_data_o.count[122] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[123] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.count[124] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[128:125] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.count[129] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[147:130] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.count[148] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[156:149] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[157] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[163:158] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[164] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[169:165] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[170] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[181:171] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[182] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[184:183] | Yes | Yes | *T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[186:185] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[199:187] | Yes | Yes | *T5,*T62,*T114 | Yes | T5,T62,T114 | OUTPUT | |
otp_lc_data_o.count[200] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[207:201] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.count[208] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[216:209] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[217] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[237:218] | Yes | Yes | *T5,*T62,*T114 | Yes | T5,T62,T114 | OUTPUT | |
otp_lc_data_o.count[238] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[248:239] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.count[250:249] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[260:251] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[261] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[268:262] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[269] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[271:270] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[272] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[275:273] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[276] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[277] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[278] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[299:279] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[300] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[306:301] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[308:307] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[311:309] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[312] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[320:313] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[321] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[330:322] | Yes | Yes | T5,*T114,*T182 | Yes | T5,T114,T177 | OUTPUT | |
otp_lc_data_o.count[331] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[332] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[333] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[348:334] | Yes | Yes | *T5,*T114,*T182 | Yes | T5,T114,T177 | OUTPUT | |
otp_lc_data_o.count[349] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[357:350] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[358] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[362:359] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.count[363] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[369:364] | Yes | Yes | *T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.count[370] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[383:371] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.state[2:0] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.state[3] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[7:4] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[9:8] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[11:10] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[12] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[14:13] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[15] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[17:16] | Yes | Yes | T62,T53,T113 | Yes | T62,T50,T176 | OUTPUT | |
otp_lc_data_o.state[18] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[24:19] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[26:25] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[37:27] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.state[38] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[58:39] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | OUTPUT | |
otp_lc_data_o.state[59] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[63:60] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.state[64] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[71:65] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[72] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[93:73] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[94] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[101:95] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.state[102] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[103] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.state[104] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[124:105] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | OUTPUT | |
otp_lc_data_o.state[125] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[129:126] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.state[130] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[133:131] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[134] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[138:135] | Yes | Yes | *T5,*T62,*T53 | Yes | T5,T62,T50 | OUTPUT | |
otp_lc_data_o.state[139] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[141:140] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.state[142] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[157:143] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[158] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[172:159] | Yes | Yes | T5,*T18,*T62 | Yes | T5,T18,T62 | OUTPUT | |
otp_lc_data_o.state[173] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[177:174] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.state[179:178] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[182:180] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[183] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[196:184] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.state[197] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[198] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[199] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[213:200] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.state[214] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[218:215] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[219] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[225:220] | Yes | Yes | T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[226] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[234:227] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[235] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[240:236] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.state[241] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[249:242] | Yes | Yes | *T4,T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.state[250] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[264:251] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.state[266:265] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[270:267] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.state[271] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[280:272] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.state[281] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[286:282] | Yes | Yes | *T62,*T113,*T173 | Yes | T62,T176,T181 | OUTPUT | |
otp_lc_data_o.state[287] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[305:288] | Yes | Yes | *T5,*T6,*T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[306] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[319:307] | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.error | Yes | Yes | T39,T63,T55 | Yes | T5,T39,T63 | OUTPUT | |
otp_lc_data_o.valid | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_keymgr_key_o.owner_seed_valid | No | No | No | OUTPUT | |||
otp_keymgr_key_o.owner_seed[255:0] | No | No | No | OUTPUT | |||
otp_keymgr_key_o.creator_seed_valid | No | No | No | OUTPUT | |||
otp_keymgr_key_o.creator_seed[255:0] | No | No | No | OUTPUT | |||
otp_keymgr_key_o.creator_root_key_share1_valid | Yes | Yes | T49,T176,T180 | Yes | T40,T109,T103 | OUTPUT | |
otp_keymgr_key_o.creator_root_key_share1[255:0] | Yes | Yes | T16,T39,T146 | Yes | T15,T82,T16 | OUTPUT | |
otp_keymgr_key_o.creator_root_key_share0_valid | Yes | Yes | T49,T176,T180 | Yes | T40,T109,T103 | OUTPUT | |
otp_keymgr_key_o.creator_root_key_share0[255:0] | Yes | Yes | T6,T147,T55 | Yes | T4,T6,T15 | OUTPUT | |
flash_otp_key_i.addr_req | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
flash_otp_key_i.data_req | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT | |
flash_otp_key_o.seed_valid | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT | |
flash_otp_key_o.rand_key[127:0] | Yes | Yes | T6,T15,T17 | Yes | T4,T6,T15 | OUTPUT | |
flash_otp_key_o.key[127:0] | Yes | Yes | T15,T82,T22 | Yes | T82,T17,T16 | OUTPUT | |
flash_otp_key_o.addr_ack | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT | |
flash_otp_key_o.data_ack | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | OUTPUT | |
sram_otp_key_i[0].req | Yes | Yes | T52,T53,T54 | Yes | T52,T53,T54 | INPUT | |
sram_otp_key_i[1].req | Yes | Yes | T183,T112,T184 | Yes | T183,T112,T184 | INPUT | |
sram_otp_key_i[2].req | Yes | Yes | T185,T186,T187 | Yes | T185,T186,T187 | INPUT | |
sram_otp_key_i[3].req | No | No | No | INPUT | |||
sram_otp_key_o[0].seed_valid | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT | |
sram_otp_key_o[0].nonce[127:0] | Yes | Yes | T6,T15,T17 | Yes | T4,T6,T15 | OUTPUT | |
sram_otp_key_o[0].key[127:0] | Yes | Yes | T15,T82,T22 | Yes | T82,T17,T16 | OUTPUT | |
sram_otp_key_o[0].ack | Yes | Yes | T52,T53,T54 | Yes | T52,T53,T54 | OUTPUT | |
sram_otp_key_o[1].seed_valid | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT | |
sram_otp_key_o[1].nonce[127:0] | Yes | Yes | T6,T15,T17 | Yes | T4,T6,T15 | OUTPUT | |
sram_otp_key_o[1].key[127:0] | Yes | Yes | T15,T82,T22 | Yes | T82,T17,T16 | OUTPUT | |
sram_otp_key_o[1].ack | Yes | Yes | T183,T112,T184 | Yes | T183,T112,T184 | OUTPUT | |
sram_otp_key_o[2].seed_valid | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT | |
sram_otp_key_o[2].nonce[127:0] | Yes | Yes | T6,T15,T17 | Yes | T4,T6,T15 | OUTPUT | |
sram_otp_key_o[2].key[127:0] | Yes | Yes | T15,T82,T22 | Yes | T82,T17,T16 | OUTPUT | |
sram_otp_key_o[2].ack | Yes | Yes | T186,T187,T188 | Yes | T186,T187,T188 | OUTPUT | |
sram_otp_key_o[3].seed_valid | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT | |
sram_otp_key_o[3].nonce[127:0] | Yes | Yes | T6,T15,T17 | Yes | T4,T6,T15 | OUTPUT | |
sram_otp_key_o[3].key[127:0] | Yes | Yes | T15,T82,T22 | Yes | T82,T17,T16 | OUTPUT | |
sram_otp_key_o[3].ack | No | No | No | OUTPUT | |||
otbn_otp_key_i.req | Yes | Yes | T82,T164,T52 | Yes | T82,T164,T52 | INPUT | |
otbn_otp_key_o.seed_valid | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT | |
otbn_otp_key_o.nonce[63:0] | Yes | Yes | T6,T15,T17 | Yes | T4,T6,T15 | OUTPUT | |
otbn_otp_key_o.key[127:0] | Yes | Yes | T15,T82,T22 | Yes | T82,T17,T16 | OUTPUT | |
otbn_otp_key_o.ack | Yes | Yes | T82,T164,T52 | Yes | T82,T164,T52 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.device_id[255:0] | Yes | Yes | T4,T15,T82 | Yes | T17,T16,T39 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[2:0] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[3] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[11:4] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[12] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[90:13] | Yes | Yes | *T185,*T189,*T116 | Yes | T185,T189,T116 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[91] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[167:92] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[168] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[193:169] | Yes | Yes | *T185,*T189,*T116 | Yes | T185,T189,T116 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[194] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[198:195] | Yes | Yes | *T185,*T189,*T116 | Yes | T185,T189,T116 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[199] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[239:200] | Yes | Yes | *T4,*T5,*T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[240] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[255:241] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0] | Yes | Yes | T6,T17,T63 | Yes | T4,T6,T15 | OUTPUT | |
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_broadcast_o.hw_cfg1_data.dis_rv_dm_late_debug[7:0] | Yes | Yes | T4,T5,T6 | Yes | T5,T6,T17 | OUTPUT | |
otp_broadcast_o.hw_cfg1_data.unallocated[39:0] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0] | Yes | Yes | T52,T62,T53 | Yes | T62,T185,T49 | OUTPUT | |
otp_broadcast_o.valid[3:0] | Yes | Yes | T5,T6,T17 | Yes | T4,T5,T6 | OUTPUT | |
otp_ext_voltage_h_io[0:0] | Excluded | Excluded | Excluded | INOUT | [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV. | ||
scan_en_i | Unreachable | Unreachable | Unreachable | INPUT | |||
scan_rst_ni | Unreachable | Unreachable | Unreachable | INPUT | |||
scanmode_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
cio_test_o[7:0] | No | No | No | OUTPUT | |||
cio_test_en_o[7:0] | Yes | Yes | T6,T17,T16 | Yes | T4,T6,T15 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |