Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T186,T188,T265
0	1	Covered	T186,T188,T265
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T186,T188,T265
1	Covered	T186,T188,T265

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T186,T188,T265
1	Covered	T186,T188,T265

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T186,T188,T265
1	1	Covered	T186,T188,T265

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T186,T188,T265
1	0	Covered	T186,T188,T265
1	1	Covered	T186,T188,T265

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T186,T188,T265

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T186,T188,T265
0	Covered	T186,T188,T265

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T186,T188,T265
0	Covered	T186,T188,T265

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	972453322	958411732	0	0
CheckNGreaterZero_A	1986	1986	0	0
GntImpliesReady_A	972453322	8385	0	0
GntImpliesValid_A	972453322	8385	0	0
GrantKnown_A	972453322	958411732	0	0
IdxKnown_A	972453322	958411732	0	0
IndexIsCorrect_A	972453322	8385	0	0
NoReadyValidNoGrant_A	972453322	0	0	0
Priority_A	972453322	8385	0	0
ReadyAndValidImplyGrant_A	972453322	8385	0	0
ReqAndReadyImplyGrant_A	972453322	8385	0	0
ReqImpliesValid_A	972453322	8385	0	0
ValidKnown_A	972453322	958411732	0	0
gen_data_port_assertion.DataFlow_A	972453322	8385	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	958411732	0	0
T4	198148	198046	0	0
T5	99264	99038	0	0
T6	376914	376696	0	0
T15	1595224	1595108	0	0
T16	1041668	1041650	0	0
T17	504358	503916	0	0
T22	950468	950344	0	0
T82	324502	324386	0	0
T83	303574	303464	0	0
T84	660200	660076	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1986	1986	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T22	2	2	0	0
T82	2	2	0	0
T83	2	2	0	0
T84	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	8385	0	0
T154	1090906	0	0	0
T186	198892	2795	0	0
T187	182630	0	0	0
T188	0	2796	0	0
T191	198434	0	0	0
T234	515980	0	0	0
T265	0	2794	0	0
T267	471036	0	0	0
T268	270420	0	0	0
T269	759554	0	0	0
T270	178122	0	0	0
T271	1354706	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	8385	0	0
T154	1090906	0	0	0
T186	198892	2795	0	0
T187	182630	0	0	0
T188	0	2796	0	0
T191	198434	0	0	0
T234	515980	0	0	0
T265	0	2794	0	0
T267	471036	0	0	0
T268	270420	0	0	0
T269	759554	0	0	0
T270	178122	0	0	0
T271	1354706	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	958411732	0	0
T4	198148	198046	0	0
T5	99264	99038	0	0
T6	376914	376696	0	0
T15	1595224	1595108	0	0
T16	1041668	1041650	0	0
T17	504358	503916	0	0
T22	950468	950344	0	0
T82	324502	324386	0	0
T83	303574	303464	0	0
T84	660200	660076	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	958411732	0	0
T4	198148	198046	0	0
T5	99264	99038	0	0
T6	376914	376696	0	0
T15	1595224	1595108	0	0
T16	1041668	1041650	0	0
T17	504358	503916	0	0
T22	950468	950344	0	0
T82	324502	324386	0	0
T83	303574	303464	0	0
T84	660200	660076	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	8385	0	0
T154	1090906	0	0	0
T186	198892	2795	0	0
T187	182630	0	0	0
T188	0	2796	0	0
T191	198434	0	0	0
T234	515980	0	0	0
T265	0	2794	0	0
T267	471036	0	0	0
T268	270420	0	0	0
T269	759554	0	0	0
T270	178122	0	0	0
T271	1354706	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	8385	0	0
T154	1090906	0	0	0
T186	198892	2795	0	0
T187	182630	0	0	0
T188	0	2796	0	0
T191	198434	0	0	0
T234	515980	0	0	0
T265	0	2794	0	0
T267	471036	0	0	0
T268	270420	0	0	0
T269	759554	0	0	0
T270	178122	0	0	0
T271	1354706	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	8385	0	0
T154	1090906	0	0	0
T186	198892	2795	0	0
T187	182630	0	0	0
T188	0	2796	0	0
T191	198434	0	0	0
T234	515980	0	0	0
T265	0	2794	0	0
T267	471036	0	0	0
T268	270420	0	0	0
T269	759554	0	0	0
T270	178122	0	0	0
T271	1354706	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	8385	0	0
T154	1090906	0	0	0
T186	198892	2795	0	0
T187	182630	0	0	0
T188	0	2796	0	0
T191	198434	0	0	0
T234	515980	0	0	0
T265	0	2794	0	0
T267	471036	0	0	0
T268	270420	0	0	0
T269	759554	0	0	0
T270	178122	0	0	0
T271	1354706	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	8385	0	0
T154	1090906	0	0	0
T186	198892	2795	0	0
T187	182630	0	0	0
T188	0	2796	0	0
T191	198434	0	0	0
T234	515980	0	0	0
T265	0	2794	0	0
T267	471036	0	0	0
T268	270420	0	0	0
T269	759554	0	0	0
T270	178122	0	0	0
T271	1354706	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	958411732	0	0
T4	198148	198046	0	0
T5	99264	99038	0	0
T6	376914	376696	0	0
T15	1595224	1595108	0	0
T16	1041668	1041650	0	0
T17	504358	503916	0	0
T22	950468	950344	0	0
T82	324502	324386	0	0
T83	303574	303464	0	0
T84	660200	660076	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972453322	8385	0	0
T154	1090906	0	0	0
T186	198892	2795	0	0
T187	182630	0	0	0
T188	0	2796	0	0
T191	198434	0	0	0
T234	515980	0	0	0
T265	0	2794	0	0
T267	471036	0	0	0
T268	270420	0	0	0
T269	759554	0	0	0
T270	178122	0	0	0
T271	1354706	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T186,T188,T265
0	1	Covered	T186,T188,T265
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T186,T188,T265
1	Covered	T186,T188,T265

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T186,T188,T265
1	Covered	T186,T188,T265

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T186,T188,T265
1	1	Covered	T186,T188,T265

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T186,T188,T265
1	0	Covered	T186,T188,T265
1	1	Covered	T186,T188,T265

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T186,T188,T265

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T186,T188,T265
0	Covered	T186,T188,T265

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T186,T188,T265
0	Covered	T186,T188,T265

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	486226661	479205866	0	0
CheckNGreaterZero_A	993	993	0	0
GntImpliesReady_A	486226661	5193	0	0
GntImpliesValid_A	486226661	5193	0	0
GrantKnown_A	486226661	479205866	0	0
IdxKnown_A	486226661	479205866	0	0
IndexIsCorrect_A	486226661	5193	0	0
NoReadyValidNoGrant_A	486226661	0	0	0
Priority_A	486226661	5193	0	0
ReadyAndValidImplyGrant_A	486226661	5193	0	0
ReqAndReadyImplyGrant_A	486226661	5193	0	0
ReqImpliesValid_A	486226661	5193	0	0
ValidKnown_A	486226661	479205866	0	0
gen_data_port_assertion.DataFlow_A	486226661	5193	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	479205866	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	993	993	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	5193	0	0
T154	545453	0	0	0
T186	99446	1731	0	0
T187	91315	0	0	0
T188	0	1732	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1730	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	5193	0	0
T154	545453	0	0	0
T186	99446	1731	0	0
T187	91315	0	0	0
T188	0	1732	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1730	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	479205866	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	479205866	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	5193	0	0
T154	545453	0	0	0
T186	99446	1731	0	0
T187	91315	0	0	0
T188	0	1732	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1730	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	5193	0	0
T154	545453	0	0	0
T186	99446	1731	0	0
T187	91315	0	0	0
T188	0	1732	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1730	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	5193	0	0
T154	545453	0	0	0
T186	99446	1731	0	0
T187	91315	0	0	0
T188	0	1732	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1730	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	5193	0	0
T154	545453	0	0	0
T186	99446	1731	0	0
T187	91315	0	0	0
T188	0	1732	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1730	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	5193	0	0
T154	545453	0	0	0
T186	99446	1731	0	0
T187	91315	0	0	0
T188	0	1732	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1730	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	479205866	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	5193	0	0
T154	545453	0	0	0
T186	99446	1731	0	0
T187	91315	0	0	0
T188	0	1732	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1730	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T186,T188,T265
0	1	Covered	T186,T188,T265
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T186,T188,T265
1	Covered	T186,T188,T265

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T186,T188,T265
1	Covered	T186,T188,T265

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T186,T188,T265
1	1	Covered	T186,T188,T265

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T186,T188,T265
1	0	Covered	T186,T188,T265
1	1	Covered	T186,T188,T265

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T186,T188,T265

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T186,T188,T265
0	Covered	T186,T188,T265

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T186,T188,T265
0	Covered	T186,T188,T265

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	486226661	479205866	0	0
CheckNGreaterZero_A	993	993	0	0
GntImpliesReady_A	486226661	3192	0	0
GntImpliesValid_A	486226661	3192	0	0
GrantKnown_A	486226661	479205866	0	0
IdxKnown_A	486226661	479205866	0	0
IndexIsCorrect_A	486226661	3192	0	0
NoReadyValidNoGrant_A	486226661	0	0	0
Priority_A	486226661	3192	0	0
ReadyAndValidImplyGrant_A	486226661	3192	0	0
ReqAndReadyImplyGrant_A	486226661	3192	0	0
ReqImpliesValid_A	486226661	3192	0	0
ValidKnown_A	486226661	479205866	0	0
gen_data_port_assertion.DataFlow_A	486226661	3192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	479205866	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	993	993	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	3192	0	0
T154	545453	0	0	0
T186	99446	1064	0	0
T187	91315	0	0	0
T188	0	1064	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1064	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	3192	0	0
T154	545453	0	0	0
T186	99446	1064	0	0
T187	91315	0	0	0
T188	0	1064	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1064	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	479205866	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	479205866	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	3192	0	0
T154	545453	0	0	0
T186	99446	1064	0	0
T187	91315	0	0	0
T188	0	1064	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1064	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	3192	0	0
T154	545453	0	0	0
T186	99446	1064	0	0
T187	91315	0	0	0
T188	0	1064	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1064	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	3192	0	0
T154	545453	0	0	0
T186	99446	1064	0	0
T187	91315	0	0	0
T188	0	1064	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1064	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	3192	0	0
T154	545453	0	0	0
T186	99446	1064	0	0
T187	91315	0	0	0
T188	0	1064	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1064	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	3192	0	0
T154	545453	0	0	0
T186	99446	1064	0	0
T187	91315	0	0	0
T188	0	1064	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1064	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	479205866	0	0
T4	99074	99023	0	0
T5	49632	49519	0	0
T6	188457	188348	0	0
T15	797612	797554	0	0
T16	520834	520825	0	0
T17	252179	251958	0	0
T22	475234	475172	0	0
T82	162251	162193	0	0
T83	151787	151732	0	0
T84	330100	330038	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486226661	3192	0	0
T154	545453	0	0	0
T186	99446	1064	0	0
T187	91315	0	0	0
T188	0	1064	0	0
T191	99217	0	0	0
T234	257990	0	0	0
T265	0	1064	0	0
T267	235518	0	0	0
T268	135210	0	0	0
T269	379777	0	0	0
T270	89061	0	0	0
T271	677353	0	0	0