Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3799437	1			T77	814		T78	88		T79	4382
values[2]	748649	1			T77	249		T78	21		T79	1880
values[3]	104905	1			T77	10		T78	11		T79	48
values[4]	55520	1			T78	1		T79	3		T83	7
values[5]	37736	1			T239	79		T434	54		T539	195
values[6]	28469	1			T239	64		T434	50		T539	132
values[7]	23291	1			T239	45		T434	35		T539	92
values[8]	20216	1			T239	35		T434	27		T539	53
values[9]	18360	1			T239	24		T434	30		T539	44
values[10]	16851	1			T239	15		T434	28		T539	33
values[11]	15641	1			T239	12		T434	12		T539	31
values[12]	14605	1			T239	20		T434	8		T539	20
values[13]	13655	1			T239	20		T434	4		T539	35
values[14]	13291	1			T239	22		T434	2		T539	25
values[15]	12443	1			T239	15		T539	27		T422	22
values[16]	12196	1			T239	6		T539	25		T422	15
values[17]	11694	1			T239	4		T539	16		T422	7
values[18]	11415	1			T239	2		T539	17		T422	2
values[19]	11128	1			T239	5		T539	11		T422	3
values[20]	10679	1			T239	4		T539	7		T422	11
values[21]	10094	1			T239	11		T539	9		T422	9
values[22]	9990	1			T239	11		T539	10		T422	15
values[23]	9743	1			T239	2		T539	6		T422	30
values[24]	9411	1			T539	11		T422	23		T436	33
values[25]	9057	1			T539	8		T422	19		T436	24
values[26]	8594	1			T539	12		T422	7		T436	18
values[27]	8224	1			T539	12		T422	5		T436	13
values[28]	7805	1			T539	9		T422	2		T436	14
values[29]	7337	1			T539	11		T422	7		T436	17
values[30]	7060	1			T539	23		T422	13		T436	18
values[31]	6269	1			T539	20		T422	10		T436	10
values[32]	5593	1			T539	12		T422	5		T436	9
values[33]	5216	1			T539	12		T422	7		T436	10
values[34]	4895	1			T539	15		T422	4		T436	11
values[35]	4502	1			T539	14		T422	2		T436	11
values[36]	4179	1			T539	14		T422	3		T436	12
values[37]	3935	1			T539	13		T422	4		T436	11
values[38]	3855	1			T539	13		T422	4		T436	12
values[39]	3701	1			T539	13		T422	6		T436	7
values[40]	3494	1			T539	7		T422	6		T436	13
values[41]	3502	1			T539	7		T422	2		T436	20
values[42]	3205	1			T539	10		T422	10		T436	12
values[43]	3143	1			T539	11		T422	8		T436	18
values[44]	3073	1			T539	10		T422	10		T436	11
values[45]	3047	1			T539	9		T422	8		T436	12
values[46]	3024	1			T539	11		T422	7		T436	18
values[47]	2910	1			T539	13		T422	6		T436	19
values[48]	2804	1			T539	6		T422	6		T436	14
values[49]	2820	1			T539	11		T422	14		T436	18
values[50]	2785	1			T539	11		T422	8		T436	14
values[51]	2774	1			T539	6		T422	4		T436	16
values[52]	2629	1			T539	11		T422	4		T436	18
values[53]	2509	1			T539	7		T422	4		T436	17
values[54]	2616	1			T539	7		T422	3		T436	15
values[55]	2570	1			T539	6		T422	5		T436	10
values[56]	2500	1			T539	10		T422	4		T436	14
values[57]	2503	1			T539	9		T422	7		T436	11
values[58]	2400	1			T539	13		T422	5		T436	16
values[59]	2342	1			T539	22		T422	3		T436	12
values[60]	2419	1			T539	20		T422	2		T436	9
values[61]	2643	1			T539	31		T422	3		T436	15
values[62]	3761	1			T539	32		T422	13		T436	29
values[63]	10156	1			T539	60		T422	15		T436	128
values[64]	216431	1			T539	284		T422	107		T436	529

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4848215	1			T77	809		T78	93		T79	5841
values[2]	814953	1			T77	235		T78	31		T79	1167
values[3]	83278	1			T77	34		T78	7		T79	132
values[4]	14653	1			T77	2		T78	2		T79	5
values[5]	5882	1			T77	1		T78	1		T83	6
values[6]	3672	1			T83	2		T538	2		T531	3
values[7]	2748	1			T531	1		T239	1		T434	6
values[8]	2262	1			T239	1		T434	18		T422	25
values[9]	1843	1			T239	3		T434	11		T422	22
values[10]	1678	1			T239	4		T434	8		T422	22
values[11]	1735	1			T239	1		T434	4		T422	19
values[12]	1597	1			T239	1		T434	1		T422	9
values[13]	1486	1			T239	1		T422	8		T436	15
values[14]	1316	1			T239	1		T422	6		T436	14
values[15]	1218	1			T239	1		T422	7		T436	18
values[16]	1163	1			T239	1		T422	6		T436	21
values[17]	1088	1			T239	1		T422	4		T436	8
values[18]	1013	1			T239	1		T422	6		T436	10
values[19]	930	1			T239	1		T422	10		T436	10
values[20]	863	1			T239	2		T422	8		T436	24
values[21]	849	1			T239	1		T422	7		T436	9
values[22]	775	1			T239	2		T436	8		T394	1
values[23]	835	1			T239	6		T436	7		T394	1
values[24]	727	1			T239	10		T436	6		T394	1
values[25]	718	1			T239	6		T436	4		T394	1
values[26]	671	1			T239	1		T436	4		T394	1
values[27]	699	1			T239	2		T436	4		T394	1
values[28]	670	1			T239	2		T436	7		T394	1
values[29]	684	1			T239	1		T436	9		T394	1
values[30]	653	1			T239	1		T436	6		T394	1
values[31]	640	1			T239	2		T436	9		T394	1
values[32]	571	1			T239	1		T436	8		T394	1
values[33]	536	1			T239	1		T436	5		T394	1
values[34]	532	1			T239	1		T436	2		T394	1
values[35]	520	1			T239	2		T436	2		T394	1
values[36]	549	1			T239	4		T436	3		T394	1
values[37]	527	1			T239	4		T436	3		T394	1
values[38]	458	1			T239	4		T436	3		T394	1
values[39]	499	1			T239	9		T436	2		T394	1
values[40]	487	1			T239	5		T436	6		T394	1
values[41]	464	1			T239	3		T436	6		T394	1
values[42]	450	1			T239	1		T436	5		T394	1
values[43]	452	1			T239	2		T436	2		T394	1
values[44]	427	1			T239	4		T436	2		T394	1
values[45]	389	1			T239	3		T436	3		T394	1
values[46]	337	1			T239	5		T436	2		T394	1
values[47]	337	1			T239	1		T436	2		T394	1
values[48]	327	1			T239	2		T436	8		T394	1
values[49]	296	1			T239	7		T436	3		T394	1
values[50]	298	1			T239	3		T436	5		T394	1
values[51]	298	1			T239	1		T436	4		T394	1
values[52]	324	1			T239	1		T436	6		T394	1
values[53]	332	1			T239	1		T436	9		T394	1
values[54]	322	1			T239	1		T436	8		T394	1
values[55]	308	1			T239	1		T436	4		T394	2
values[56]	324	1			T239	1		T436	3		T394	1
values[57]	292	1			T239	2		T436	2		T394	1
values[58]	275	1			T239	2		T436	3		T394	1
values[59]	330	1			T239	2		T436	2		T394	1
values[60]	287	1			T239	5		T436	2		T394	1
values[61]	317	1			T239	1		T436	4		T394	1
values[62]	506	1			T239	6		T436	18		T394	1
values[63]	1774	1			T239	28		T436	50		T394	1
values[64]	21265	1			T239	50		T436	65		T394	218

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	583988	1			T77	14		T78	1		T79	275
values[2]	2686452	1			T77	363		T78	110		T79	3500
values[3]	1221313	1			T77	698		T78	75		T79	2380
values[4]	147550	1			T77	18		T78	6		T79	382
values[5]	75470	1			T79	183		T83	1		T538	2
values[6]	48529	1			T79	79		T531	2		T239	82
values[7]	35501	1			T79	23		T239	55		T434	39
values[8]	28435	1			T79	6		T239	37		T434	48
values[9]	23517	1			T239	34		T434	48		T539	87
values[10]	21150	1			T239	11		T434	44		T539	96
values[11]	19713	1			T239	10		T434	20		T539	82
values[12]	18038	1			T239	11		T434	25		T539	79
values[13]	17279	1			T239	10		T434	32		T539	70
values[14]	16367	1			T239	10		T434	25		T539	49
values[15]	15303	1			T239	9		T434	12		T539	45
values[16]	14554	1			T239	25		T434	5		T539	24
values[17]	13953	1			T239	15		T434	3		T539	15
values[18]	13588	1			T239	7		T539	20		T422	9
values[19]	13123	1			T239	9		T539	12		T422	6
values[20]	12536	1			T239	8		T539	13		T422	6
values[21]	12277	1			T239	6		T539	18		T422	4
values[22]	11531	1			T239	6		T539	17		T422	5
values[23]	11029	1			T239	9		T539	8		T422	4
values[24]	10566	1			T239	12		T539	14		T422	2
values[25]	10351	1			T239	5		T539	16		T422	3
values[26]	9551	1			T239	5		T539	12		T422	5
values[27]	9359	1			T239	11		T539	17		T422	2
values[28]	8644	1			T239	4		T539	21		T422	7
values[29]	8295	1			T239	3		T539	24		T422	10
values[30]	7434	1			T239	5		T539	19		T422	6
values[31]	6977	1			T239	1		T539	13		T422	2
values[32]	6393	1			T239	1		T539	9		T422	6
values[33]	6009	1			T239	3		T539	12		T422	4
values[34]	5470	1			T239	3		T539	10		T422	3
values[35]	5226	1			T239	2		T539	9		T422	6
values[36]	4814	1			T239	2		T539	10		T422	10
values[37]	4380	1			T239	1		T539	27		T422	22
values[38]	4227	1			T239	1		T539	19		T422	13
values[39]	3949	1			T239	1		T539	10		T422	8
values[40]	3644	1			T239	4		T539	12		T422	3
values[41]	3512	1			T239	2		T539	14		T422	4
values[42]	3561	1			T239	1		T539	10		T422	8
values[43]	3582	1			T239	3		T539	27		T422	6
values[44]	3437	1			T239	2		T539	12		T422	7
values[45]	3307	1			T239	1		T539	12		T422	3
values[46]	3266	1			T239	2		T539	21		T422	2
values[47]	3298	1			T239	1		T539	18		T422	5
values[48]	3271	1			T239	1		T539	19		T422	5
values[49]	3171	1			T239	1		T539	26		T422	10
values[50]	3201	1			T239	3		T539	20		T422	7
values[51]	3168	1			T239	3		T539	13		T422	5
values[52]	3084	1			T239	1		T539	7		T422	4
values[53]	3065	1			T239	1		T539	11		T422	9
values[54]	3097	1			T239	1		T539	17		T422	7
values[55]	2964	1			T239	3		T539	17		T422	4
values[56]	2870	1			T239	5		T539	17		T422	10
values[57]	2807	1			T239	4		T539	20		T422	11
values[58]	2637	1			T239	3		T539	11		T422	6
values[59]	2643	1			T239	2		T539	16		T422	7
values[60]	2669	1			T239	1		T539	19		T422	7
values[61]	2723	1			T239	1		T539	16		T422	5
values[62]	3493	1			T239	1		T539	22		T422	5
values[63]	8562	1			T239	11		T539	60		T422	5
values[64]	208248	1			T239	28		T539	195		T422	52