Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2118904	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33849854

1

T4

36883

T5

17465

T17

17187

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	24465502	1			T4	25664		T5	13310		T17	7192
values[0x0]	9681998	1			T4	11219		T5	4155		T17	9995
values[0x1]	1821258	1			T4	2512		T5	3769		T17	1233

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	488328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35480430

1

T4

39395

T5

21234

T17

18420

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16984689	1			T4	19698		T5	10617		T17	9210
valid_sources[0x01]	16983644	1			T4	19697		T5	10617		T17	9210
valid_sources[0x02]	33128	1			T82	4		T193	1		T61	1
valid_sources[0x03]	31823	1			T81	1		T193	2		T131	60
valid_sources[0x04]	33054	1			T81	2		T131	84		T540	614
valid_sources[0x05]	31804	1			T81	1		T82	1		T192	1
valid_sources[0x06]	31640	1			T192	3		T131	53		T540	621
valid_sources[0x07]	32116	1			T81	2		T131	24		T540	725
valid_sources[0x08]	32094	1			T82	1		T61	1		T131	136
valid_sources[0x09]	31811	1			T81	1		T192	4		T131	85
valid_sources[0x0a]	30858	1			T193	1		T131	101		T540	510
valid_sources[0x0b]	31689	1			T61	6		T131	83		T540	463
valid_sources[0x0c]	32923	1			T131	62		T540	714		T347	76
valid_sources[0x0d]	32070	1			T193	3		T61	1		T131	83
valid_sources[0x0e]	31940	1			T193	1		T61	1		T131	91
valid_sources[0x0f]	32947	1			T81	1		T82	1		T131	115
valid_sources[0x10]	31789	1			T81	1		T82	2		T61	8
valid_sources[0x11]	32464	1			T81	1		T131	79		T540	642
valid_sources[0x12]	32754	1			T81	4		T82	1		T131	128
valid_sources[0x13]	32226	1			T81	1		T82	1		T131	87
valid_sources[0x14]	31429	1			T131	33		T540	504		T347	73
valid_sources[0x15]	32920	1			T131	77		T540	524		T347	87
valid_sources[0x16]	31601	1			T61	3		T131	154		T540	466
valid_sources[0x17]	32185	1			T81	1		T131	66		T540	578
valid_sources[0x18]	32331	1			T131	62		T540	637		T347	88
valid_sources[0x19]	33109	1			T81	1		T131	66		T540	427
valid_sources[0x1a]	31671	1			T193	2		T61	3		T131	45
valid_sources[0x1b]	31774	1			T81	1		T82	4		T192	4
valid_sources[0x1c]	32108	1			T82	3		T131	67		T540	493
valid_sources[0x1d]	32307	1			T131	125		T540	537		T347	85
valid_sources[0x1e]	31898	1			T193	2		T61	2		T131	67
valid_sources[0x1f]	33503	1			T82	2		T193	2		T131	36
valid_sources[0x20]	32240	1			T81	1		T82	1		T193	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23949590

1

T4

25664

T5

13310

T17

7192

values[0x0]

all_enables

biggest_size

9644503

1

T4

11219

T5

4155

T17

9995

values[0x1]

all_enables

biggest_size

255761

1

T72

22

T81

19

T82

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2957627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

466664

1

T77

141

T78

20

T79

861

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1158513	1			T77	349		T78	42		T79	2069
values[0x0]	1105727	1			T77	335		T78	38		T79	2069
values[0x1]	1160051	1			T77	389		T78	41		T79	2175

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2291212	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1133079

1

T77

364

T78

45

T79

2100

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52911	1			T77	23		T79	90		T83	26
valid_sources[0x01]	53615	1			T77	14		T79	130		T83	31
valid_sources[0x02]	53292	1			T77	12		T79	79		T83	11
valid_sources[0x03]	54807	1			T77	18		T79	94		T83	10
valid_sources[0x04]	53647	1			T77	14		T78	2		T79	114
valid_sources[0x05]	52999	1			T77	15		T79	105		T83	21
valid_sources[0x06]	54250	1			T77	15		T79	86		T83	10
valid_sources[0x07]	53278	1			T77	19		T78	7		T79	76
valid_sources[0x08]	52516	1			T77	20		T79	109		T83	28
valid_sources[0x09]	54589	1			T77	17		T79	116		T83	36
valid_sources[0x0a]	53072	1			T77	18		T79	109		T83	52
valid_sources[0x0b]	52680	1			T77	14		T78	2		T79	105
valid_sources[0x0c]	53909	1			T77	23		T79	100		T83	33
valid_sources[0x0d]	52530	1			T77	16		T78	6		T79	97
valid_sources[0x0e]	54373	1			T77	20		T78	1		T79	83
valid_sources[0x0f]	53672	1			T77	14		T79	115		T83	18
valid_sources[0x10]	54045	1			T77	14		T79	111		T83	4
valid_sources[0x11]	53662	1			T77	20		T78	5		T79	82
valid_sources[0x12]	53001	1			T77	19		T79	93		T83	11
valid_sources[0x13]	54478	1			T77	17		T79	89		T83	10
valid_sources[0x14]	53900	1			T77	14		T78	4		T79	80
valid_sources[0x15]	53926	1			T77	15		T79	110		T83	25
valid_sources[0x16]	55099	1			T77	23		T78	3		T79	113
valid_sources[0x17]	52884	1			T77	16		T79	88		T83	41
valid_sources[0x18]	53246	1			T77	10		T78	2		T79	112
valid_sources[0x19]	54195	1			T77	16		T78	7		T79	101
valid_sources[0x1a]	53766	1			T77	17		T78	1		T79	92
valid_sources[0x1b]	52978	1			T77	16		T78	4		T79	106
valid_sources[0x1c]	52236	1			T77	13		T79	101		T83	12
valid_sources[0x1d]	52431	1			T77	18		T79	115		T83	20
valid_sources[0x1e]	54722	1			T77	21		T79	93		T83	27
valid_sources[0x1f]	52820	1			T77	15		T79	120		T83	44
valid_sources[0x20]	53316	1			T77	24		T78	2		T79	86

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48962

1

T77

17

T78

3

T79

82

values[0x0]

all_enables

biggest_size

368309

1

T77

102

T78

13

T79

690

values[0x1]

all_enables

biggest_size

49393

1

T77

22

T78

4

T79

89

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3157759	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

515092

1

T77

153

T78

21

T79

1015

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1256108	1			T77	367		T78	48		T79	2404
values[0x0]	1159575	1			T77	344		T78	46		T79	2329
values[0x1]	1257168	1			T77	370		T78	40		T79	2412

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2423527	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1249324

1

T77

366

T78

50

T79

2411

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57343	1			T77	3		T79	146		T83	16
valid_sources[0x01]	58282	1			T77	23		T78	2		T79	126
valid_sources[0x02]	57173	1			T77	10		T78	2		T79	109
valid_sources[0x03]	56811	1			T77	21		T78	3		T79	96
valid_sources[0x04]	57837	1			T77	18		T79	145		T83	16
valid_sources[0x05]	58044	1			T77	8		T78	2		T79	115
valid_sources[0x06]	57478	1			T77	19		T78	2		T79	131
valid_sources[0x07]	57101	1			T77	20		T79	134		T83	25
valid_sources[0x08]	57048	1			T77	17		T79	81		T83	20
valid_sources[0x09]	57796	1			T77	25		T78	2		T79	80
valid_sources[0x0a]	57493	1			T77	15		T78	3		T79	107
valid_sources[0x0b]	57641	1			T77	13		T79	120		T83	26
valid_sources[0x0c]	56617	1			T77	20		T78	1		T79	119
valid_sources[0x0d]	57284	1			T77	14		T78	2		T79	95
valid_sources[0x0e]	58511	1			T77	13		T79	103		T83	25
valid_sources[0x0f]	57305	1			T77	18		T78	1		T79	118
valid_sources[0x10]	57630	1			T77	20		T79	123		T83	27
valid_sources[0x11]	57266	1			T77	19		T78	2		T79	117
valid_sources[0x12]	57081	1			T77	26		T78	5		T79	91
valid_sources[0x13]	58639	1			T77	21		T79	116		T83	28
valid_sources[0x14]	56882	1			T77	23		T79	116		T83	20
valid_sources[0x15]	58021	1			T77	16		T78	5		T79	128
valid_sources[0x16]	57023	1			T77	28		T78	1		T79	111
valid_sources[0x17]	57085	1			T77	18		T78	5		T79	109
valid_sources[0x18]	57512	1			T77	13		T78	5		T79	122
valid_sources[0x19]	57313	1			T77	18		T78	2		T79	119
valid_sources[0x1a]	57820	1			T77	14		T78	1		T79	109
valid_sources[0x1b]	57323	1			T77	15		T79	112		T83	18
valid_sources[0x1c]	56236	1			T77	7		T78	4		T79	117
valid_sources[0x1d]	57148	1			T77	28		T79	130		T83	21
valid_sources[0x1e]	57568	1			T77	28		T78	6		T79	109
valid_sources[0x1f]	57786	1			T77	22		T79	155		T83	24
valid_sources[0x20]	56463	1			T77	17		T78	9		T79	111

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53769

1

T77

17

T78

1

T79

114

values[0x0]

all_enables

biggest_size

407505

1

T77

118

T78

19

T79

807

values[0x1]

all_enables

biggest_size

53818

1

T77

18

T78

1

T79

94

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2988771	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

473769

1

T77

146

T78

32

T79

928

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1172300	1			T77	358		T78	61		T79	2237
values[0x0]	1119006	1			T77	361		T78	62		T79	2277
values[0x1]	1171234	1			T77	374		T78	69		T79	2314

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2313907	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1148633

1

T77

368

T78

71

T79

2252

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54778	1			T77	14		T78	3		T79	101
valid_sources[0x01]	54528	1			T77	21		T78	1		T79	148
valid_sources[0x02]	53877	1			T77	10		T78	2		T79	102
valid_sources[0x03]	53616	1			T77	18		T78	4		T79	102
valid_sources[0x04]	54607	1			T77	19		T78	4		T79	97
valid_sources[0x05]	54376	1			T77	32		T78	3		T79	104
valid_sources[0x06]	54306	1			T77	13		T78	1		T79	104
valid_sources[0x07]	53591	1			T77	19		T78	7		T79	92
valid_sources[0x08]	53775	1			T77	15		T79	94		T83	22
valid_sources[0x09]	54090	1			T77	18		T78	4		T79	103
valid_sources[0x0a]	54549	1			T77	11		T78	3		T79	102
valid_sources[0x0b]	53697	1			T77	18		T78	1		T79	108
valid_sources[0x0c]	53462	1			T77	22		T78	2		T79	117
valid_sources[0x0d]	53767	1			T77	13		T79	90		T83	31
valid_sources[0x0e]	55017	1			T77	20		T78	1		T79	95
valid_sources[0x0f]	54166	1			T77	19		T78	1		T79	125
valid_sources[0x10]	53738	1			T77	17		T78	6		T79	122
valid_sources[0x11]	53788	1			T77	16		T78	4		T79	97
valid_sources[0x12]	52902	1			T77	20		T78	6		T79	98
valid_sources[0x13]	54255	1			T77	19		T78	4		T79	81
valid_sources[0x14]	53768	1			T77	13		T78	3		T79	111
valid_sources[0x15]	54372	1			T77	19		T78	2		T79	113
valid_sources[0x16]	54435	1			T77	15		T78	4		T79	124
valid_sources[0x17]	53910	1			T77	15		T78	3		T79	95
valid_sources[0x18]	54273	1			T77	12		T78	5		T79	105
valid_sources[0x19]	54145	1			T77	12		T78	1		T79	116
valid_sources[0x1a]	54024	1			T77	21		T78	3		T79	93
valid_sources[0x1b]	53935	1			T77	15		T78	2		T79	118
valid_sources[0x1c]	54153	1			T77	14		T78	1		T79	106
valid_sources[0x1d]	53742	1			T77	17		T78	7		T79	138
valid_sources[0x1e]	53845	1			T77	12		T78	4		T79	73
valid_sources[0x1f]	53497	1			T77	14		T78	4		T79	168
valid_sources[0x20]	53820	1			T77	15		T78	4		T79	88

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49522

1

T77

12

T78

8

T79

100

values[0x0]

all_enables

biggest_size

374763

1

T77

125

T78

20

T79

742

values[0x1]

all_enables

biggest_size

49484

1

T77

9

T78

4

T79

86