Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_dm	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_dm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	88.53		89.15			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	86	86	100.00
Total Bits	938	938	100.00
Total Bits 0->1	469	469	100.00
Total Bits 1->0	469	469	100.00

Ports	86	86	100.00
Port Bits	938	938	100.00
Port Bits 0->1	469	469	100.00
Port Bits 1->0	469	469	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_lc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
rst_lc_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
next_dm_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
otp_dis_rv_dm_late_debug_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T17,T20,T45	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
ndmreset_req_o	Yes	Yes	T7,T80,T8	Yes	T7,T80,T8	OUTPUT
dmactive_o	Yes	Yes	T72,T235,T81	Yes	T59,T71,T72	OUTPUT
debug_req_o	Yes	Yes	T80,T247,T248	Yes	T80,T247,T248	OUTPUT
unavailable_i	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.d_ready	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_address[3:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_address[20:4]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[21]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_address[23:22]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[24]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[30]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_source[5:0]	Yes	Yes	T77,*T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	OUTPUT
regs_tl_d_o.d_sink	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	OUTPUT
regs_tl_d_o.d_source[5:0]	Yes	Yes	T77,T79,T83	Yes	T77,T78,T79	OUTPUT
regs_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T79,T83	OUTPUT
regs_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T79,T83	OUTPUT
regs_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	INPUT
mem_tl_d_i.a_address[11:0]	Yes	Yes	T77,T78,*T79	Yes	T77,T78,T79	INPUT
mem_tl_d_i.a_address[15:12]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_address[16]	Yes	Yes	*T80,*T247,*T192	Yes	T80,T247,T192	INPUT
mem_tl_d_i.a_address[31:17]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_source[5:0]	Yes	Yes	*T80,*T247,*T248	Yes	T80,T247,T248	INPUT
mem_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
mem_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T4,T5,T17	Yes	T17,T20,T45	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T80,T247,T248	Yes	T80,T247,T248	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T17,T20,T45	OUTPUT
mem_tl_d_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
mem_tl_d_o.d_source[5:0]	Yes	Yes	*T80,*T247,*T248	Yes	T80,T247,T248	OUTPUT
mem_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
mem_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T17,T20,T45	OUTPUT
mem_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	OUTPUT
sba_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	OUTPUT
sba_tl_h_o.a_address[31:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
sba_tl_h_o.a_source[5:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
sba_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
sba_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
sba_tl_h_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
sba_tl_h_i.d_source[5:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
sba_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
sba_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_opcode[0]	Yes	Yes	*T59,*T71,*T72	Yes	T59,T71,T72	INPUT
sba_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_valid	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T84,T85,T684	Yes	T84,T85,T684	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T84,T85,T684	Yes	T84,T85,T684	OUTPUT
jtag_i.tdi	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	INPUT
jtag_i.trst_n	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	INPUT
jtag_i.tms	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	INPUT
jtag_i.tck	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	INPUT
jtag_o.tdo_oe	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	OUTPUT
jtag_o.tdo	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	OUTPUT

*Tests covering at least one bit in the range