Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	477516129	53612503	0	0
DepthKnown_A	477516129	477411701	0	0
RvalidKnown_A	477516129	477411701	0	0
WreadyKnown_A	477516129	477411701	0	0
gen_passthru_fifo.paramCheckPass	987	987	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	53612503	0	0
T4	347353	42724	0	0
T5	225333	23031	0	0
T6	39678	0	0	0
T17	299918	36346	0	0
T18	127489	12724	0	0
T19	202521	22297	0	0
T20	50999	1608	0	0
T21	168910	24764	0	0
T45	415405	60053	0	0
T62	95117	15427	0	0
T150	0	25435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	477516129	41354676	0	0
DepthKnown_A	477516129	477411701	0	0
RvalidKnown_A	477516129	477411701	0	0
WreadyKnown_A	477516129	477411701	0	0
gen_passthru_fifo.paramCheckPass	987	987	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	41354676	0	0
T4	347353	32932	0	0
T5	225333	19106	0	0
T6	39678	0	0	0
T17	299918	28502	0	0
T18	127489	8869	0	0
T19	202521	18323	0	0
T20	50999	925	0	0
T21	168910	16383	0	0
T45	415405	51252	0	0
T62	95117	9888	0	0
T150	0	19904	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	477516129	39307503	0	0
DepthKnown_A	477516129	477411701	0	0
RvalidKnown_A	477516129	477411701	0	0
WreadyKnown_A	477516129	477411701	0	0
gen_passthru_fifo.paramCheckPass	987	987	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	39307503	0	0
T4	347353	42003	0	0
T5	225333	21439	0	0
T6	39678	0	0	0
T17	299918	18815	0	0
T18	127489	8425	0	0
T19	202521	17484	0	0
T20	50999	310	0	0
T21	168910	12899	0	0
T45	415405	43369	0	0
T62	95117	6004	0	0
T150	0	13989	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	477516129	33976882	0	0
DepthKnown_A	477516129	477411701	0	0
RvalidKnown_A	477516129	477411701	0	0
WreadyKnown_A	477516129	477411701	0	0
gen_passthru_fifo.paramCheckPass	987	987	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	33976882	0	0
T4	347353	39395	0	0
T5	225333	21234	0	0
T6	39678	0	0	0
T17	299918	18420	0	0
T18	127489	8245	0	0
T19	202521	16663	0	0
T20	50999	235	0	0
T21	168910	12220	0	0
T45	415405	42955	0	0
T62	95117	5813	0	0
T150	0	13731	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550308132	88132	0	0
DepthKnown_A	550308132	550191522	0	0
RvalidKnown_A	550308132	550191522	0	0
WreadyKnown_A	550308132	550191522	0	0
gen_passthru_fifo.paramCheckPass	2877	2877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	88132	0	0
T4	347353	14	0	0
T5	225333	53	0	0
T6	39678	0	0	0
T17	299918	68	0	0
T18	127489	15	0	0
T19	202521	22	0	0
T20	50999	3	0	0
T21	168910	34	0	0
T45	415405	48	0	0
T62	95117	17	0	0
T150	0	115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877	2877	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550308132	90814	0	0
DepthKnown_A	550308132	550191522	0	0
RvalidKnown_A	550308132	550191522	0	0
WreadyKnown_A	550308132	550191522	0	0
gen_passthru_fifo.paramCheckPass	2877	2877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	90814	0	0
T4	347353	14	0	0
T5	225333	53	0	0
T6	39678	0	0	0
T17	299918	68	0	0
T18	127489	15	0	0
T19	202521	22	0	0
T20	50999	3	0	0
T21	168910	34	0	0
T45	415405	48	0	0
T62	95117	17	0	0
T150	0	115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877	2877	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550308132	50859	0	0
DepthKnown_A	550308132	550191522	0	0
RvalidKnown_A	550308132	550191522	0	0
WreadyKnown_A	550308132	550191522	0	0
gen_passthru_fifo.paramCheckPass	2877	2877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	50859	0	0
T4	347353	13	0	0
T5	225333	52	0	0
T6	39678	0	0	0
T17	299918	59	0	0
T18	127489	12	0	0
T19	202521	19	0	0
T20	50999	3	0	0
T21	168910	32	0	0
T45	415405	41	0	0
T62	95117	12	0	0
T150	0	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877	2877	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550308132	50859	0	0
DepthKnown_A	550308132	550191522	0	0
RvalidKnown_A	550308132	550191522	0	0
WreadyKnown_A	550308132	550191522	0	0
gen_passthru_fifo.paramCheckPass	2877	2877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	50859	0	0
T4	347353	13	0	0
T5	225333	52	0	0
T6	39678	0	0	0
T17	299918	59	0	0
T18	127489	12	0	0
T19	202521	19	0	0
T20	50999	3	0	0
T21	168910	32	0	0
T45	415405	41	0	0
T62	95117	12	0	0
T150	0	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877	2877	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550308132	37273	0	0
DepthKnown_A	550308132	550191522	0	0
RvalidKnown_A	550308132	550191522	0	0
WreadyKnown_A	550308132	550191522	0	0
gen_passthru_fifo.paramCheckPass	2877	2877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	37273	0	0
T4	347353	1	0	0
T5	225333	1	0	0
T6	39678	0	0	0
T17	299918	9	0	0
T18	127489	3	0	0
T19	202521	3	0	0
T20	50999	0	0	0
T21	168910	2	0	0
T45	415405	7	0	0
T62	95117	5	0	0
T123	0	3	0	0
T150	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877	2877	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550308132	39955	0	0
DepthKnown_A	550308132	550191522	0	0
RvalidKnown_A	550308132	550191522	0	0
WreadyKnown_A	550308132	550191522	0	0
gen_passthru_fifo.paramCheckPass	2877	2877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	39955	0	0
T4	347353	1	0	0
T5	225333	1	0	0
T6	39678	0	0	0
T17	299918	9	0	0
T18	127489	3	0	0
T19	202521	3	0	0
T20	50999	0	0	0
T21	168910	2	0	0
T45	415405	7	0	0
T62	95117	5	0	0
T123	0	3	0	0
T150	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550308132	550191522	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877	2877	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0