Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	88.53		89.15			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	88.53		89.15			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	88.53		89.15			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	88.53		89.15			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T115,T206	Yes	T5,T115,T206	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T115,T206	Yes	T5,T115,T206	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	INPUT
tl_i.a_valid	Yes	Yes	T5,T62,T115	Yes	T5,T62,T115	INPUT
tl_o.a_ready	Yes	Yes	T5,T62,T115	Yes	T5,T62,T115	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T115,T206	Yes	T5,T115,T206	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T115,T206	Yes	T5,T62,T115	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T115,T206	Yes	T5,T62,T115	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T115,*T206	Yes	T5,T115,T206	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T62,T115	Yes	T5,T62,T115	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T338,T84	Yes	T62,T338,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T153	Yes	T84,T85,T153	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T153	Yes	T84,T85,T153	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T338,T84	Yes	T62,T338,T84	OUTPUT
cio_rx_i	Yes	Yes	T5,T17,T45	Yes	T4,T5,T17	INPUT
cio_tx_o	Yes	Yes	T5,T115,T206	Yes	T5,T115,T206	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T115,T206	Yes	T5,T115,T206	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T115,T206	Yes	T5,T115,T206	OUTPUT
intr_rx_watermark_o	Yes	Yes	T5,T115,T206	Yes	T5,T115,T206	OUTPUT
intr_tx_done_o	Yes	Yes	T5,T115,T206	Yes	T5,T115,T206	OUTPUT
intr_rx_overflow_o	Yes	Yes	T5,T115,T206	Yes	T5,T115,T206	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_break_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_timeout_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T54,T57,T58	Yes	T54,T57,T58	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T54,T57,T58	Yes	T54,T57,T58	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	INPUT
tl_i.a_valid	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	INPUT
tl_o.a_ready	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	OUTPUT
tl_o.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T54,T57,T58	Yes	T54,T57,T58	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T54,T57,T58	Yes	T62,T54,T57	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T54,T57,T58	Yes	T62,T54,T57	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T54,*T57,*T58	Yes	T54,T57,T58	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T84,T85	Yes	T62,T84,T85	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T153	Yes	T84,T85,T153	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T153	Yes	T84,T85,T153	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T84,T85	Yes	T62,T84,T85	OUTPUT
cio_rx_i	Yes	Yes	T17,T45,T21	Yes	T4,T5,T17	INPUT
cio_tx_o	Yes	Yes	T54,T57,T58	Yes	T54,T57,T58	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T209,T287,T309	Yes	T209,T287,T309	OUTPUT
intr_tx_empty_o	Yes	Yes	T209,T287,T309	Yes	T209,T287,T309	OUTPUT
intr_rx_watermark_o	Yes	Yes	T209,T287,T309	Yes	T209,T287,T309	OUTPUT
intr_tx_done_o	Yes	Yes	T315,T209,T287	Yes	T315,T209,T287	OUTPUT
intr_rx_overflow_o	Yes	Yes	T315,T209,T287	Yes	T315,T209,T287	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_break_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_timeout_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	INPUT
tl_i.a_valid	Yes	Yes	T62,T115,T206	Yes	T62,T115,T206	INPUT
tl_o.a_ready	Yes	Yes	T62,T115,T206	Yes	T62,T115,T206	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T115,T206,T207	Yes	T62,T115,T206	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T115,T206,T207	Yes	T62,T115,T206	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T115,*T206,*T207	Yes	T115,T206,T207	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T62,T115,T206	Yes	T62,T115,T206	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T84,T384	Yes	T62,T84,T384	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T84,T384	Yes	T62,T84,T384	OUTPUT
cio_rx_i	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	INPUT
cio_tx_o	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	OUTPUT
intr_tx_empty_o	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	OUTPUT
intr_rx_watermark_o	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	OUTPUT
intr_tx_done_o	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	OUTPUT
intr_rx_overflow_o	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_break_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_timeout_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	INPUT
tl_i.a_valid	Yes	Yes	T5,T62,T144	Yes	T5,T62,T144	INPUT
tl_o.a_ready	Yes	Yes	T5,T62,T144	Yes	T5,T62,T144	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T144,T116	Yes	T5,T62,T144	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T144,T116	Yes	T5,T62,T144	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T144,*T116	Yes	T5,T144,T116	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T62,T144	Yes	T5,T62,T144	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T338,T84	Yes	T62,T338,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T338,T84	Yes	T62,T338,T84	OUTPUT
cio_rx_i	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	INPUT
cio_tx_o	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	OUTPUT
intr_rx_watermark_o	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	OUTPUT
intr_tx_done_o	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	OUTPUT
intr_rx_overflow_o	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_break_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_timeout_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	INPUT
tl_i.a_valid	Yes	Yes	T62,T30,T88	Yes	T62,T30,T88	INPUT
tl_o.a_ready	Yes	Yes	T62,T30,T88	Yes	T62,T30,T88	OUTPUT
tl_o.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T30,T88,T236	Yes	T62,T30,T88	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T30,T88,T236	Yes	T62,T30,T88	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T30,*T88,*T299	Yes	T30,T88,T299	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T62,T30,T88	Yes	T62,T30,T88	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T84,T85	Yes	T62,T84,T85	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T84,T85	Yes	T62,T84,T85	OUTPUT
cio_rx_i	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	INPUT
cio_tx_o	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	OUTPUT
intr_tx_empty_o	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	OUTPUT
intr_rx_watermark_o	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	OUTPUT
intr_tx_done_o	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	OUTPUT
intr_rx_overflow_o	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_break_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_timeout_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T287,T301,T302	Yes	T287,T301,T302	OUTPUT

*Tests covering at least one bit in the range