Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_lc_or_hardened

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_lc_or_hardened

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.27	94.12	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.27	94.12	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	3	3

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	4	4

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	8883	8883	0	0
OutputsKnown_A	1793286297	1788473191	0	0
gen_flops.OutputDelay_A	1434034566	1431152568	0	17676
gen_no_flops.OutputDelay_A	359251731	357278481	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8883	8883	0	0
T4	9	9	0	0
T5	9	9	0	0
T6	9	9	0	0
T17	9	9	0	0
T18	9	9	0	0
T19	9	9	0	0
T20	9	9	0	0
T21	9	9	0	0
T45	9	9	0	0
T62	9	9	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1793286297	1788473191	0	0
T4	1349038	1345317	0	0
T5	836898	831728	0	0
T6	156916	153642	0	0
T17	1114728	1111270	0	0
T18	474869	471714	0	0
T19	750506	747751	0	0
T20	198465	193816	0	0
T21	632954	626484	0	0
T45	1608209	1605455	0	0
T62	356890	352482	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434034566	1431152568	0	17676
T4	1068610	1066416	0	18
T5	671370	668348	0	18
T6	123676	121728	0	18
T17	894060	891868	0	18
T18	380630	378756	0	18
T19	602450	600802	0	18
T20	157122	154324	0	18
T21	506468	502620	0	0
T45	1275038	1273316	0	18
T62	285466	282870	0	18
T150	0	0	0	18

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359251731	357278481	0	0
T4	280428	278877	0	0
T5	165528	163356	0	0
T6	33240	31890	0	0
T17	220668	219330	0	0
T18	94239	92934	0	0
T19	148056	146925	0	0
T20	41343	39444	0	0
T21	126486	123816	0	0
T45	333171	332091	0	0
T62	71424	69588	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	987	987	0	0
OutputsKnown_A	119750577	119092827	0	0
gen_flops.OutputDelay_A	119750577	119086003	0	2946

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119092827	0	0
T4	93476	92959	0	0
T5	55176	54452	0	0
T6	11080	10630	0	0
T17	73556	73110	0	0
T18	31413	30978	0	0
T19	49352	48975	0	0
T20	13781	13148	0	0
T21	42162	41272	0	0
T45	111057	110697	0	0
T62	23808	23196	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119086003	0	2946
T4	93476	92955	0	3
T5	55176	54448	0	3
T6	11080	10626	0	3
T17	73556	73098	0	3
T18	31413	30974	0	3
T19	49352	48971	0	3
T20	13781	13140	0	3
T21	42162	41264	0	0
T45	111057	110689	0	3
T62	23808	23192	0	3
T150	0	0	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	987	987	0	0
OutputsKnown_A	119750577	119092827	0	0
gen_flops.OutputDelay_A	119750577	119086003	0	2946

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119092827	0	0
T4	93476	92959	0	0
T5	55176	54452	0	0
T6	11080	10630	0	0
T17	73556	73110	0	0
T18	31413	30978	0	0
T19	49352	48975	0	0
T20	13781	13148	0	0
T21	42162	41272	0	0
T45	111057	110697	0	0
T62	23808	23196	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119086003	0	2946
T4	93476	92955	0	3
T5	55176	54448	0	3
T6	11080	10626	0	3
T17	73556	73098	0	3
T18	31413	30974	0	3
T19	49352	48971	0	3
T20	13781	13140	0	3
T21	42162	41264	0	0
T45	111057	110689	0	3
T62	23808	23192	0	3
T150	0	0	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	987	987	0	0
OutputsKnown_A	119750577	119092827	0	0
gen_flops.OutputDelay_A	119750577	119086003	0	2946

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119092827	0	0
T4	93476	92959	0	0
T5	55176	54452	0	0
T6	11080	10630	0	0
T17	73556	73110	0	0
T18	31413	30978	0	0
T19	49352	48975	0	0
T20	13781	13148	0	0
T21	42162	41272	0	0
T45	111057	110697	0	0
T62	23808	23196	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119086003	0	2946
T4	93476	92955	0	3
T5	55176	54448	0	3
T6	11080	10626	0	3
T17	73556	73098	0	3
T18	31413	30974	0	3
T19	49352	48971	0	3
T20	13781	13140	0	3
T21	42162	41264	0	0
T45	111057	110689	0	3
T62	23808	23192	0	3
T150	0	0	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	987	987	0	0
OutputsKnown_A	119750577	119092827	0	0
gen_flops.OutputDelay_A	119750577	119086003	0	2946

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119092827	0	0
T4	93476	92959	0	0
T5	55176	54452	0	0
T6	11080	10630	0	0
T17	73556	73110	0	0
T18	31413	30978	0	0
T19	49352	48975	0	0
T20	13781	13148	0	0
T21	42162	41272	0	0
T45	111057	110697	0	0
T62	23808	23196	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119086003	0	2946
T4	93476	92955	0	3
T5	55176	54448	0	3
T6	11080	10626	0	3
T17	73556	73098	0	3
T18	31413	30974	0	3
T19	49352	48971	0	3
T20	13781	13140	0	3
T21	42162	41264	0	0
T45	111057	110689	0	3
T62	23808	23192	0	3
T150	0	0	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	4	4

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	987	987	0	0
OutputsKnown_A	119750577	119092827	0	0
gen_no_flops.OutputDelay_A	119750577	119092827	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119092827	0	0
T4	93476	92959	0	0
T5	55176	54452	0	0
T6	11080	10630	0	0
T17	73556	73110	0	0
T18	31413	30978	0	0
T19	49352	48975	0	0
T20	13781	13148	0	0
T21	42162	41272	0	0
T45	111057	110697	0	0
T62	23808	23196	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119092827	0	0
T4	93476	92959	0	0
T5	55176	54452	0	0
T6	11080	10630	0	0
T17	73556	73110	0	0
T18	31413	30978	0	0
T19	49352	48975	0	0
T20	13781	13148	0	0
T21	42162	41272	0	0
T45	111057	110697	0	0
T62	23808	23196	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	4	4

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	987	987	0	0
OutputsKnown_A	119750577	119092827	0	0
gen_no_flops.OutputDelay_A	119750577	119092827	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119092827	0	0
T4	93476	92959	0	0
T5	55176	54452	0	0
T6	11080	10630	0	0
T17	73556	73110	0	0
T18	31413	30978	0	0
T19	49352	48975	0	0
T20	13781	13148	0	0
T21	42162	41272	0	0
T45	111057	110697	0	0
T62	23808	23196	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119092827	0	0
T4	93476	92959	0	0
T5	55176	54452	0	0
T6	11080	10630	0	0
T17	73556	73110	0	0
T18	31413	30978	0	0
T19	49352	48975	0	0
T20	13781	13148	0	0
T21	42162	41272	0	0
T45	111057	110697	0	0
T62	23808	23196	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	3	3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	987	987	0	0
OutputsKnown_A	119750577	119092827	0	0
gen_no_flops.OutputDelay_A	119750577	119092827	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119092827	0	0
T4	93476	92959	0	0
T5	55176	54452	0	0
T6	11080	10630	0	0
T17	73556	73110	0	0
T18	31413	30978	0	0
T19	49352	48975	0	0
T20	13781	13148	0	0
T21	42162	41272	0	0
T45	111057	110697	0	0
T62	23808	23196	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119750577	119092827	0	0
T4	93476	92959	0	0
T5	55176	54452	0	0
T6	11080	10630	0	0
T17	73556	73110	0	0
T18	31413	30978	0	0
T19	49352	48975	0	0
T20	13781	13148	0	0
T21	42162	41272	0	0
T45	111057	110697	0	0
T62	23808	23196	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	987	987	0	0
OutputsKnown_A	477516129	477411701	0	0
gen_flops.OutputDelay_A	477516129	477404278	0	2946

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477404278	0	2946
T4	347353	347298	0	3
T5	225333	225278	0	3
T6	39678	39612	0	3
T17	299918	299738	0	3
T18	127489	127430	0	3
T19	202521	202459	0	3
T20	50999	50882	0	3
T21	168910	168782	0	0
T45	415405	415280	0	3
T62	95117	95051	0	3
T150	0	0	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	987	987	0	0
OutputsKnown_A	477516129	477411701	0	0
gen_flops.OutputDelay_A	477516129	477404278	0	2946

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477411701	0	0
T4	347353	347302	0	0
T5	225333	225282	0	0
T6	39678	39616	0	0
T17	299918	299750	0	0
T18	127489	127434	0	0
T19	202521	202463	0	0
T20	50999	50890	0	0
T21	168910	168790	0	0
T45	415405	415288	0	0
T62	95117	95055	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	477404278	0	2946
T4	347353	347298	0	3
T5	225333	225278	0	3
T6	39678	39612	0	3
T17	299918	299738	0	3
T18	127489	127430	0	3
T19	202521	202459	0	3
T20	50999	50882	0	3
T21	168910	168782	0	0
T45	415405	415280	0	3
T62	95117	95051	0	3
T150	0	0	0	3