Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	88.53		89.15			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T78,T79,T239	Yes	T78,T79,T239	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T169,T210,T103	Yes	T169,T210,T103	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T169,T210,T103	Yes	T169,T210,T103	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T81,T79,T240	Yes	T81,T79,T240	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T81,T77,T78	Yes	T81,T77,T78	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T59,*T71,*T72	Yes	T59,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T59,T71,T72	Yes	T59,T71,T72	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T77,*T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T77,T79,T83	Yes	T77,T78,T79	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T79,T83	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T79,T83	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T80,*T247,*T248	Yes	T80,T247,T248	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T17	Yes	T17,T20,T45	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T80,T247,T248	Yes	T80,T247,T248	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T17,T20,T45	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T80,*T247,*T248	Yes	T80,T247,T248	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T17,T20,T45	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T80,T247,T192	Yes	T80,T247,T192	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T59,T71,T54	Yes	T59,T71,T54	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T54,T57,T58	Yes	T54,T57,T58	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T17,T62,T20	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T263,T264	Yes	T62,T263,T264	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T62,T263,T264	Yes	T62,T263,T264	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T62,T263,T264	Yes	T62,T263,T264	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T62,T263,T264	Yes	T62,T263,T264	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T62,T263,T264	Yes	T62,T263,T264	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T263,T264,T265	Yes	T263,T264,T265	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T62,T63,T64	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T263,T264,T265	Yes	T62,T263,T264	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T77,T78,*T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T263,*T264,*T386	Yes	T263,T264,T386	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T62,T263,T264	Yes	T62,T263,T264	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_peri_i.d_error	Yes	Yes	T67,T169,T210	Yes	T67,T169,T210	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_peri_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T62,T150,T26	Yes	T62,T150,T26	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T62,T150,T26	Yes	T62,T150,T26	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T150,T26	Yes	T62,T150,T26	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T62,T150,T26	Yes	T62,T150,T26	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T62,T150,T26	Yes	T62,T150,T26	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T62,T150,T26	Yes	T62,T150,T26	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T192,*T193,*T77	Yes	T192,T193,T77	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T26,T188,T189	Yes	T26,T188,T189	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T62,T150,T26	Yes	T62,T150,T26	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T62,T150,T26	Yes	T62,T150,T26	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T150,T26,T27	Yes	T150,T26,T27	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T150,T26,T27	Yes	T62,T150,T26	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T150,T26,T27	Yes	T150,T26,T27	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T192,*T193,*T77	Yes	T192,T193,T77	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T150,*T26,*T27	Yes	T150,T26,T27	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T62,T150,T26	Yes	T62,T150,T26	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T62,T150,T365	Yes	T62,T150,T365	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T62,T150,T365	Yes	T62,T150,T365	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T150,T365	Yes	T62,T150,T365	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T62,T150,T365	Yes	T62,T150,T365	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T62,T150,T365	Yes	T62,T150,T365	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T62,T150,T365	Yes	T62,T150,T365	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T192,*T193,T77	Yes	T192,T193,T77	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T62,T150,T365	Yes	T62,T150,T365	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T62,T150,T365	Yes	T62,T150,T365	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T150,T365,T376	Yes	T150,T365,T376	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T150,T365,T376	Yes	T62,T150,T365	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T150,T365,T376	Yes	T150,T365,T376	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T192,*T193,T77	Yes	T192,T193,T77	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T150,*T365,*T376	Yes	T150,T365,T376	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T62,T150,T365	Yes	T62,T150,T365	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T62,T31,T2	Yes	T62,T31,T2	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T62,T31,T2	Yes	T62,T31,T2	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T31,T2	Yes	T62,T31,T2	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T62,T31,T2	Yes	T62,T31,T2	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T62,T31,T2	Yes	T62,T31,T2	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T62,T31,T2	Yes	T62,T31,T2	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T62,T31,T2	Yes	T62,T31,T2	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T62,T31,T2	Yes	T62,T31,T2	INPUT
tl_usbdev_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T32,T365,T287	Yes	T32,T365,T287	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T365,T287	Yes	T32,T365,T287	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T62,T31,T2	Yes	T31,T2,T32	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T62,*T31,*T2	Yes	T31,T2,T32	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T62,T31,T2	Yes	T62,T31,T2	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T192,*T77,*T78	Yes	T192,T77,T78	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T17,T20,T45	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T17,T18	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T192,*T77,*T79	Yes	T192,T77,T78	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T192,T77,T78	Yes	T192,T77,T78	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T192,T77,T78	Yes	T192,T77,T78	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T192,T77,T78	Yes	T192,T77,T78	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T192,T77,T78	Yes	T192,T77,T78	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T192,T77,T79	Yes	T192,T77,T79	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T192,T77,T78	Yes	T192,T77,T78	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T192,T77,T78	Yes	T192,T77,T78	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T192,T77,T78	Yes	T192,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T192,T77,T78	Yes	T192,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T192,T77,T78	Yes	T192,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T192,T77,T78	Yes	T192,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T192,T77,T78	Yes	T192,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T192,*T77,*T78	Yes	T192,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T192,T77,T78	Yes	T192,T77,T78	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T17,T20,T45	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_hmac_o.d_ready	Yes	Yes	T17,T62,T20	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T62,T246,T54	Yes	T62,T246,T54	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T246,T54	Yes	T62,T246,T54	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T62,T246,T54	Yes	T62,T246,T54	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T62,T246,T54	Yes	T62,T246,T54	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T62,T246,T54	Yes	T62,T246,T54	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T192,*T77,*T78	Yes	T192,T77,T78	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T327,T683,T280	Yes	T327,T683,T280	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T62,T246,T54	Yes	T62,T246,T54	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T62,T246,T54	Yes	T62,T246,T54	INPUT
tl_hmac_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T246,T54,T57	Yes	T246,T54,T57	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T246,T54,T57	Yes	T246,T54,T57	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T62,T246,T54	Yes	T246,T54,T57	INPUT
tl_hmac_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T192,*T77,*T78	Yes	T192,T77,T78	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T62,*T246,*T54	Yes	T246,T54,T57	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T62,T246,T54	Yes	T62,T246,T54	INPUT
tl_kmac_o.d_ready	Yes	Yes	T17,T62,T20	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T62,T150,T112	Yes	T62,T150,T112	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T62,T150,T112	Yes	T62,T150,T112	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T192,*T61,*T77	Yes	T192,T61,T77	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T112,T385,T211	Yes	T112,T385,T211	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	INPUT
tl_kmac_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T45,T21,T150	Yes	T45,T21,T150	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T21,T150	Yes	T45,T21,T150	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T62,T45,T21	Yes	T21,T150,T112	INPUT
tl_kmac_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T192,*T61,*T77	Yes	T192,T61,T77	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T62,*T45,*T21	Yes	T21,T150,T112	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	INPUT
tl_aes_o.d_ready	Yes	Yes	T17,T62,T20	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T62,T45,T659	Yes	T62,T45,T659	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T45,T659	Yes	T62,T45,T659	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T62,T45,T659	Yes	T62,T45,T659	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T62,T45,T659	Yes	T62,T45,T659	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T62,T45,T659	Yes	T62,T45,T659	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T62,T45,T659	Yes	T62,T45,T659	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T62,T45,T659	Yes	T62,T45,T659	INPUT
tl_aes_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T45,T659,T102	Yes	T45,T659,T102	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T659,T102	Yes	T62,T45,T659	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T659,T102,T681	Yes	T62,T45,T659	INPUT
tl_aes_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T78,T79	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T45,*T659,*T102	Yes	T45,T659,T102	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T62,T45,T659	Yes	T62,T45,T659	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T192,*T77,*T78	Yes	T192,T77,T78	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T79,T83	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T45,T246,T119	Yes	T45,T246,T119	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T192,*T77,*T79	Yes	T192,T77,T78	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T45,*T246,*T119	Yes	T45,T246,T119	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T62,T45,T246	Yes	T62,T45,T246	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T192,*T77,*T78	Yes	T192,T77,T78	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_csrng_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T45,T246,T119	Yes	T45,T246,T119	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_csrng_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T79,T83	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T192,*T77,*T79	Yes	T192,T77,T79	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T79,T83	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T45,*T246,*T119	Yes	T45,T246,T119	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T62,T45,T246	Yes	T62,T45,T246	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T62,T45,T246	Yes	T62,T45,T246	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T192,*T77,*T78	Yes	T192,T77,T78	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_edn0_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T45,T246,T119	Yes	T45,T246,T119	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_edn0_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T192,*T77,*T79	Yes	T192,T77,T78	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T45,*T246,*T119	Yes	T45,T246,T119	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_edn1_o.d_ready	Yes	Yes	T17,T62,T20	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T62,T45,T246	Yes	T62,T45,T246	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T45,T246	Yes	T62,T45,T246	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T62,T45,T246	Yes	T62,T45,T246	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T62,T45,T246	Yes	T62,T45,T246	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T62,T45,T246	Yes	T62,T45,T246	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T192,*T77,*T78	Yes	T192,T77,T78	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T62,T45,T246	Yes	T62,T45,T246	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T62,T45,T246	Yes	T62,T45,T246	INPUT
tl_edn1_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T45,T246,T119	Yes	T45,T246,T119	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T246,T119	Yes	T62,T45,T246	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T45,T246,T119	Yes	T62,T45,T246	INPUT
tl_edn1_i.d_sink	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T192,*T77,*T79	Yes	T192,T77,T78	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T77,T79,T83	Yes	T77,T78,T79	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T45,*T246,*T119	Yes	T45,T246,T119	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T62,T45,T246	Yes	T62,T45,T246	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T5,T17,T62	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T5,T62,T18	Yes	T5,T62,T18	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T62,T18	Yes	T5,T62,T18	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T5,T62,T18	Yes	T5,T62,T18	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T5,T62,T18	Yes	T5,T62,T18	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T5,T62,T18	Yes	T5,T62,T18	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T192,*T193,*T77	Yes	T192,T193,T77	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T5,T62,T18	Yes	T5,T62,T18	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T5,T62,T18	Yes	T5,T62,T18	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T5,T19,T150	Yes	T5,T19,T150	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T18,T19	Yes	T5,T62,T18	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T5,T19,T150	Yes	T5,T62,T18	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T192,*T193,*T77	Yes	T192,T193,T77	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T5,*T18,*T19	Yes	T5,T18,T19	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T5,T62,T18	Yes	T5,T62,T18	INPUT
tl_otbn_o.d_ready	Yes	Yes	T17,T62,T20	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T62,T45,T150	Yes	T62,T45,T150	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T45,T150	Yes	T62,T45,T150	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T62,T45,T150	Yes	T62,T45,T150	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T62,T45,T150	Yes	T62,T45,T150	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T62,T45,T150	Yes	T62,T45,T150	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T72,*T81,*T82	Yes	T72,T81,T82	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T62,T45,T150	Yes	T62,T45,T150	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T62,T45,T150	Yes	T62,T45,T150	INPUT
tl_otbn_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T45,T150,T119	Yes	T45,T150,T119	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T150,T119	Yes	T45,T150,T119	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T62,T45,T150	Yes	T45,T150,T119	INPUT
tl_otbn_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T72,*T81,*T82	Yes	T72,T81,T82	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T62,*T45,*T150	Yes	T45,T150,T119	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T62,T45,T150	Yes	T62,T45,T150	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T17,T62,T20	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T192,*T77,*T79	Yes	T192,T77,T79	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	INPUT
tl_keymgr_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T45,T21,T150	Yes	T45,T21,T150	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T21,T150	Yes	T62,T45,T21	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T45,T21,T122	Yes	T62,T45,T21	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T192,*T77,*T78	Yes	T192,T77,T78	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T45,*T21,*T150	Yes	T45,T21,T150	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T62,T45,T21	Yes	T62,T45,T21	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T17,T62,T20	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T192,*T193,*T77	Yes	T192,T193,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T79,T83,T240	Yes	T78,T79,T83	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T173,T192,T193	Yes	T173,T192,T193	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T113,T55	Yes	T62,T54,T57	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T54,T113,T55	Yes	T62,T54,T57	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T192,*T193,*T77	Yes	T192,T193,T77	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T113,*T170,*T114	Yes	T113,T170,T114	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T17,T20,T45	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range