Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T32,T87,T36 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T31,T2,T32 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T32,T23,T24 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T31,T2,T32 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T32,T23,T24 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T17 |
1 | 0 | Covered | T43,T44,T181 |
1 | 1 | Covered | T32,T23,T24 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T43,T44,T181 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T32,T23,T24 |
1 | 1 | Covered | T43,T44,T181 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T32,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T43,T44,T181 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T32,T23,T24 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T32,T36,T74 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T32,T36,T25 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T32,T36,T25 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T17 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T32,T36,T25 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T32,T36,T25 |
1 | 1 | Covered | T42,T43,T44 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T32,T36,T25 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 2 | 66.67 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 0 | 0.00 |
CONT_ASSIGN | 102 | 0 | 0 | |
CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
0 |
1 |
102 |
|
unreachable |
114 |
1 |
1 |
115 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 4 | 2 | 50.00 |
Logical | 4 | 2 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
LINE 114
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
1 |
50.00 |
TERNARY |
114 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 114 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 2 | 66.67 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 0 | 0.00 |
CONT_ASSIGN | 102 | 0 | 0 | |
CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
0 |
1 |
102 |
|
unreachable |
114 |
1 |
1 |
115 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 4 | 2 | 50.00 |
Logical | 4 | 2 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
LINE 114
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
1 |
50.00 |
TERNARY |
114 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 114 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T72,T26,T27 |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T27,T28 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T44,T181 |
1 | 1 | Covered | T26,T27,T28 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T27,T28 |
1 | 1 | Covered | T42,T43,T44 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T26,T27,T28 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T26,T27,T28 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T27,T28 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T27,T28 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T72,T26,T27 |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T28,T188 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T23,T24,T42 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T23,T24,T42 |
1 | 1 | Covered | T42,T43,T44 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T23,T24,T42 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T23,T24,T42 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T23,T24,T42 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T27,T28 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T72,T26,T81 |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T23,T188 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T23,T25,T42 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T23,T25,T42 |
1 | 1 | Covered | T42,T43,T44 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T23,T25,T42 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T23,T25,T42 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T23,T25,T42 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T27,T28 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T72,T26,T81 |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Covered | T42,T44,T181 |
1 | 1 | Covered | T42,T44,T181 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T23,T188 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T23,T25,T42 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T23,T25,T42 |
1 | 1 | Covered | T42,T43,T44 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T23,T25,T42 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T23,T25,T42 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T23,T25,T42 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T27,T28 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T72,T26,T27 |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T27,T28 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T26,T27,T28 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T27,T28 |
1 | 1 | Covered | T42,T43,T44 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T26,T27,T28 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T26,T27,T28 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T27,T46,T47 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T27,T28 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T27,T46,T47 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T72,T26,T27 |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T26,T27,T28 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T26,T27,T28 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T27,T28 |
1 | 1 | Covered | T42,T43,T44 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T26,T27,T28 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T26,T27,T28 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T27,T46,T47 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T27,T28 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T27,T46,T47 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T26,T88,T89 |
0 | 1 | Covered | T26,T88,T89 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T28,T23 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T44,T181 |
1 | 1 | Covered | T26,T28,T23 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T44,T181 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T28,T23 |
1 | 1 | Covered | T42,T44,T181 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T26,T28,T23 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T44,T181 |
1 | 1 | Covered | T26,T28,T23 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T44,T181 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T28,T23 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T26,T88,T89 |
0 | 1 | Covered | T26,T88,T89 |
1 | 0 | Covered | T42,T44,T181 |
1 | 1 | Covered | T42,T43,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T88,T89 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T26,T88,T89 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T88,T89 |
1 | 1 | Covered | T42,T43,T44 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T26,T88,T89 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T26,T88,T89 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T88,T89 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T26,T88,T89 |
0 | 1 | Covered | T26,T188,T16 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T28,T188 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T43,T44,T181 |
1 | 1 | Covered | T26,T23,T188 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T23,T188 |
1 | 1 | Covered | T42,T43,T44 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T26,T23,T188 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T26,T23,T188 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T23,T188 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T26,T88,T89 |
0 | 1 | Covered | T26,T188,T24 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T28,T188 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T26,T23,T188 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T26,T23,T188 |
1 | 1 | Covered | T42,T43,T44 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T26,T23,T188 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T26,T23,T188 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T23,T188 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 57 | 0 | 0 | |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
57 |
|
unreachable |
64 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 64
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 66
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T26,T88,T89 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 71
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 71 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 57 | 0 | 0 | |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
57 |
|
unreachable |
64 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 64
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 66
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T26,T88,T89 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 71
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 71 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
|
unreachable |
51 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T33,T34,T195 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T33,T34,T35 |
1 | 1 | Covered | T42,T43,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T16,T11 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42,T43,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T48,T49,T50 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T48,T49,T50 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T42,T43,T44 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T3,T16,T11 |
1 | Covered | T4,T5,T6 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T16,T11 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T4,T5,T6 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
78 |
2 |
2 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T3,T16,T11 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
AnalogNoScan_A |
987 |
987 |
0 |
0 |
AnalogNoScan_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
987 |
987 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T62 |
1 |
1 |
0 |
0 |