Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	88.53		89.15			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T17,T20,T45	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_main_o.d_error	Yes	Yes	T67,T169,T210	Yes	T67,T169,T210	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_main_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T54,T57,T58	Yes	T54,T57,T58	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T54,T57,T58	Yes	T54,T57,T58	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	INPUT
tl_uart0_i.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T54,T57,T58	Yes	T54,T57,T58	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T57,T58	Yes	T62,T54,T57	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T54,T57,T58	Yes	T62,T54,T57	INPUT
tl_uart0_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T78,T79	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T54,*T57,*T58	Yes	T54,T57,T58	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T62,T115,T206	Yes	T62,T115,T206	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T62,T115,T206	Yes	T62,T115,T206	INPUT
tl_uart1_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T115,T206,T207	Yes	T115,T206,T207	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T115,T206,T207	Yes	T62,T115,T206	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T115,T206,T207	Yes	T62,T115,T206	INPUT
tl_uart1_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T115,*T206,*T207	Yes	T115,T206,T207	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T62,T115,T206	Yes	T62,T115,T206	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T5,T62,T144	Yes	T5,T62,T144	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T5,T62,T144	Yes	T5,T62,T144	INPUT
tl_uart2_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T5,T144,T116	Yes	T5,T144,T116	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T144,T116	Yes	T5,T62,T144	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T5,T144,T116	Yes	T5,T62,T144	INPUT
tl_uart2_i.d_sink	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T78,T79	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T5,*T144,*T116	Yes	T5,T144,T116	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T5,T62,T144	Yes	T5,T62,T144	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T62,T30,T88	Yes	T62,T30,T88	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T62,T30,T88	Yes	T62,T30,T88	INPUT
tl_uart3_i.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T30,T88,T299	Yes	T30,T88,T299	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T88,T236	Yes	T62,T30,T88	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T30,T88,T236	Yes	T62,T30,T88	INPUT
tl_uart3_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T78,T79	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T30,*T88,*T299	Yes	T30,T88,T299	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T62,T30,T88	Yes	T62,T30,T88	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T246,T298,T205	Yes	T246,T298,T205	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T246,T298,T205	Yes	T246,T298,T205	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T62,T246,T298	Yes	T62,T246,T298	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T62,T246,T298	Yes	T62,T246,T298	INPUT
tl_i2c0_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T246,T298,T205	Yes	T246,T298,T205	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T246,T298,T205	Yes	T62,T246,T298	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T246,T298,T205	Yes	T62,T246,T298	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T192,*T77,*T78	Yes	T192,T77,T78	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T246,*T298,*T205	Yes	T246,T298,T205	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T62,T246,T298	Yes	T62,T246,T298	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T19,T246,T298	Yes	T19,T246,T298	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T19,T246,T298	Yes	T19,T246,T298	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T62,T19,T246	Yes	T62,T19,T246	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T62,T19,T246	Yes	T62,T19,T246	INPUT
tl_i2c1_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T19,T246,T298	Yes	T19,T246,T298	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T246,T298	Yes	T62,T19,T246	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T19,T246,T298	Yes	T62,T19,T246	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T192,*T77,*T79	Yes	T192,T77,T79	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T19,*T246,*T298	Yes	T19,T246,T298	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T62,T19,T246	Yes	T62,T19,T246	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T246,T208,T298	Yes	T246,T208,T298	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T246,T208,T298	Yes	T246,T208,T298	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T62,T246,T208	Yes	T62,T246,T208	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T62,T246,T208	Yes	T62,T246,T208	INPUT
tl_i2c2_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T79,T83	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T246,T208,T298	Yes	T246,T208,T298	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T246,T208,T298	Yes	T62,T246,T208	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T246,T208,T298	Yes	T62,T246,T208	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T79,T83	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T192,*T77,*T79	Yes	T192,T77,T78	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T246,*T208,*T298	Yes	T246,T208,T298	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T62,T246,T208	Yes	T62,T246,T208	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T150,T329,T330	Yes	T150,T329,T330	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T150,T329,T330	Yes	T150,T329,T330	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T62,T150,T329	Yes	T62,T150,T329	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T62,T150,T329	Yes	T62,T150,T329	INPUT
tl_pattgen_i.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T150,T329,T330	Yes	T150,T329,T330	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T150,T329,T330	Yes	T62,T150,T329	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T150,T329,T330	Yes	T62,T150,T329	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T61,T77,T79	Yes	T61,T77,T78	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T150,*T329,*T330	Yes	T150,T329,T330	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T62,T150,T329	Yes	T62,T150,T329	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T145,T396,T682	Yes	T145,T396,T682	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T145,T396,T682	Yes	T145,T396,T682	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T62,T145,T396	Yes	T62,T145,T396	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T62,T145,T396	Yes	T62,T145,T396	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T145,T396,T682	Yes	T145,T396,T682	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T145,T396,T682	Yes	T62,T145,T396	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T145,T396,T682	Yes	T62,T145,T396	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T145,*T396,*T682	Yes	T145,T396,T682	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T62,T145,T396	Yes	T62,T145,T396	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_gpio_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T29,T246,T298	Yes	T29,T246,T298	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T246,T298	Yes	T62,T29,T246	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T29,T246,T298	Yes	T62,T29,T246	INPUT
tl_gpio_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T192,*T77,*T79	Yes	T192,T77,T78	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T17,*T62,*T45	Yes	T4,T5,T17	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T150,T26,T88	Yes	T150,T26,T88	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T150,T26,T88	Yes	T150,T26,T88	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T62,T150,T26	Yes	T62,T150,T26	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T62,T150,T26	Yes	T62,T150,T26	INPUT
tl_spi_device_i.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T150,T26,T88	Yes	T150,T26,T88	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T150,T26,T88	Yes	T150,T26,T88	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T62,T150,T26	Yes	T150,T26,T88	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T192,*T193,*T77	Yes	T192,T193,T77	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T62,*T150,*T26	Yes	T150,T26,T88	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T62,T150,T26	Yes	T62,T150,T26	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T150,T244,T145	Yes	T150,T244,T145	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T150,T244,T145	Yes	T150,T244,T145	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T62,T150,T244	Yes	T62,T150,T244	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T62,T150,T244	Yes	T62,T150,T244	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T150,T244,T245	Yes	T150,T244,T245	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T150,T244,T145	Yes	T62,T150,T244	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T244,T145,T245	Yes	T62,T150,T244	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T192,*T193,*T77	Yes	T192,T193,T77	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T150,*T244,*T145	Yes	T150,T244,T145	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T62,T150,T244	Yes	T62,T150,T244	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T18,T150,T123	Yes	T18,T150,T123	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T18,T150,T123	Yes	T18,T150,T123	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T62,T18,T45	Yes	T62,T18,T45	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T62,T18,T45	Yes	T62,T18,T45	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T18,T150,T123	Yes	T18,T150,T123	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T150,T123	Yes	T62,T18,T45	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T18,T123,T338	Yes	T62,T18,T45	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T78,T79	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T18,*T150,*T123	Yes	T18,T150,T123	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T62,T18,T45	Yes	T62,T18,T45	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T45,T21	Yes	T4,T5,T17	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T17,T45,T21	Yes	T4,T5,T17	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T77,T79,T83	Yes	T77,T78,T79	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T78,T79	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T62,T60	Yes	T5,T62,T60	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T60,T115	Yes	T5,T60,T115	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T17,T20	Yes	T4,T5,T17	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T17,T20	Yes	T4,T5,T17	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T77,T79,T83	Yes	T77,T78,T79	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T78,T79	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T77,T79,T83	Yes	T77,T78,T79	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T5,*T60,*T115	Yes	T5,T60,T115	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T61,*T77,*T79	Yes	T61,T77,T78	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T147,*T148,*T149	Yes	T147,T148,T149	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T62,*T45,*T21	Yes	T45,T21,T150	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T61,T77,T78	Yes	T61,T77,T78	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T61,T77,T78	Yes	T61,T77,T78	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T61,T77,T78	Yes	T61,T77,T78	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T5,T17	Yes	T17,T20,T45	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T61,T77,T78	Yes	T61,T77,T78	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T61,T77,T78	Yes	T61,T77,T78	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T17,T20,T45	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T61,T77,T79	Yes	T61,T77,T78	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T17,T20,T45	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T61,T77,T78	Yes	T61,T77,T78	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T62,T21,T22	Yes	T62,T21,T22	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T62,T21,T22	Yes	T62,T21,T22	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T62,T21,T22	Yes	T62,T21,T22	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T62,T21,T22	Yes	T62,T21,T22	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T77,T79,T83	Yes	T77,T78,T79	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T21,T22,T54	Yes	T21,T22,T294	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T22,T65,T166	Yes	T62,T22,T65	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T21,T22,T54	Yes	T62,T21,T22	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T80,*T61,*T295	Yes	T80,T61,T295	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T79,T83	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T21,*T22,*T54	Yes	T21,T22,T115	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T62,T21,T22	Yes	T62,T21,T22	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T79,T83	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T17,T150,T54	Yes	T17,T150,T54	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T150,T54	Yes	T17,T62,T150	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T77,T79,T83	Yes	T77,T78,T79	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T192,*T193,*T77	Yes	T192,T193,T77	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T77,T79,T83	Yes	T77,T78,T79	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T17,*T62,*T20	Yes	T4,T5,T17	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T17,T62,T45	Yes	T17,T62,T45	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T17,T62,T45	Yes	T17,T62,T45	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T17,T62,T45	Yes	T17,T62,T45	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T17,T62,T45	Yes	T17,T62,T45	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T17,T62,T45	Yes	T17,T62,T45	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T62,T45	Yes	T17,T62,T45	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T17,T123,T338	Yes	T17,T62,T45	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T17,*T62,*T45	Yes	T17,T62,T45	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T17,T62,T45	Yes	T17,T62,T45	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T54,T57,T58	Yes	T54,T57,T58	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T54,T57,T58	Yes	T54,T57,T58	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T113,T170,T114	Yes	T113,T170,T114	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T113,T55	Yes	T62,T54,T57	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T54,T113,T55	Yes	T62,T54,T57	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T192,*T193,*T77	Yes	T192,T193,T77	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T113,*T170,*T114	Yes	T113,T170,T114	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T62,T54,T57	Yes	T62,T54,T57	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T17,T18,T45	Yes	T17,T18,T45	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T17,T20,T45	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T17,T18,T45	Yes	T17,T18,T45	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T20,T18	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T17,T45,T123	Yes	T17,T45,T123	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T72,*T81,*T82	Yes	T72,T81,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T18,T123,T338	Yes	T18,T123,T338	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T18,T123,T338	Yes	T18,T123,T338	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T62,T18,T123	Yes	T62,T18,T123	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T62,T18,T123	Yes	T62,T18,T123	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T18,T123,T338	Yes	T18,T123,T338	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T123,T338	Yes	T62,T18,T123	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T18,T123,T338	Yes	T62,T18,T123	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T247,T248,T688	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T18,*T123,*T338	Yes	T18,T123,T338	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T62,T18,T123	Yes	T62,T18,T123	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T66,T439,T48	Yes	T66,T439,T48	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T66,T439,T48	Yes	T66,T439,T48	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T62,T66,T439	Yes	T62,T66,T439	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T62,T66,T439	Yes	T62,T66,T439	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T66,T439,T48	Yes	T66,T439,T48	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T66,T439,T48	Yes	T62,T66,T439	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T66,T439,T48	Yes	T62,T66,T439	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T192,*T193,*T77	Yes	T192,T193,T77	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T66,*T439,*T48	Yes	T66,T439,T48	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T62,T66,T439	Yes	T62,T66,T439	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T246,T298,T107	Yes	T246,T298,T107	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T246,T298,T107	Yes	T246,T298,T107	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T62,T246,T298	Yes	T62,T246,T298	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T62,T246,T298	Yes	T62,T246,T298	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T77,T78,T83	Yes	T77,T78,T83	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T246,T298,T107	Yes	T246,T298,T107	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T246,T298,T107	Yes	T62,T246,T298	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T107,T2,T7	Yes	T62,T246,T298	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T77,*T79,*T83	Yes	T77,T78,T79	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T77,T79,T83	Yes	T77,T79,T83	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T246,*T298,*T107	Yes	T246,T298,T107	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T62,T246,T298	Yes	T62,T246,T298	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T72,*T80,*T81	Yes	T72,T80,T81	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T72,T81,T82	Yes	T72,T81,T82	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_ast_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T17,T20,T45	Yes	T4,T5,T17	INPUT
tl_ast_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range