Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.27	94.12	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	955032258	4047	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	955032258	4047	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	955032258	4047	0	0
T4	347353	1	0	0
T5	225333	1	0	0
T6	39678	0	0	0
T17	299918	6	0	0
T18	127489	2	0	0
T19	202521	2	0	0
T20	50999	0	0	0
T21	168910	2	0	0
T45	415405	3	0	0
T62	95117	1	0	0
T120	330081	0	0	0
T123	0	2	0	0
T124	142682	0	0	0
T150	0	2	0	0
T171	68843	9	0	0
T172	0	8	0	0
T174	0	8	0	0
T205	264302	0	0	0
T250	120234	0	0	0
T263	392304	0	0	0
T281	378540	0	0	0
T282	154125	0	0	0
T283	79090	0	0	0
T288	0	8	0	0
T289	0	11	0	0
T290	0	8	0	0
T291	277957	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	955032258	4047	0	0
T4	347353	1	0	0
T5	225333	1	0	0
T6	39678	0	0	0
T17	299918	6	0	0
T18	127489	2	0	0
T19	202521	2	0	0
T20	50999	0	0	0
T21	168910	2	0	0
T45	415405	3	0	0
T62	95117	1	0	0
T120	330081	0	0	0
T123	0	2	0	0
T124	142682	0	0	0
T150	0	2	0	0
T171	68843	9	0	0
T172	0	8	0	0
T174	0	8	0	0
T205	264302	0	0	0
T250	120234	0	0	0
T263	392304	0	0	0
T281	378540	0	0	0
T282	154125	0	0	0
T283	79090	0	0	0
T288	0	8	0	0
T289	0	11	0	0
T290	0	8	0	0
T291	277957	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	477516129	52	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	477516129	52	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	52	0	0
T120	330081	0	0	0
T124	142682	0	0	0
T171	68843	9	0	0
T172	0	8	0	0
T174	0	8	0	0
T205	264302	0	0	0
T250	120234	0	0	0
T263	392304	0	0	0
T281	378540	0	0	0
T282	154125	0	0	0
T283	79090	0	0	0
T288	0	8	0	0
T289	0	11	0	0
T290	0	8	0	0
T291	277957	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	52	0	0
T120	330081	0	0	0
T124	142682	0	0	0
T171	68843	9	0	0
T172	0	8	0	0
T174	0	8	0	0
T205	264302	0	0	0
T250	120234	0	0	0
T263	392304	0	0	0
T281	378540	0	0	0
T282	154125	0	0	0
T283	79090	0	0	0
T288	0	8	0	0
T289	0	11	0	0
T290	0	8	0	0
T291	277957	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	477516129	3995	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	477516129	3995	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	3995	0	0
T4	347353	1	0	0
T5	225333	1	0	0
T6	39678	0	0	0
T17	299918	6	0	0
T18	127489	2	0	0
T19	202521	2	0	0
T20	50999	0	0	0
T21	168910	2	0	0
T45	415405	3	0	0
T62	95117	1	0	0
T123	0	2	0	0
T150	0	2	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	477516129	3995	0	0
T4	347353	1	0	0
T5	225333	1	0	0
T6	39678	0	0	0
T17	299918	6	0	0
T18	127489	2	0	0
T19	202521	2	0	0
T20	50999	0	0	0
T21	168910	2	0	0
T45	415405	3	0	0
T62	95117	1	0	0
T123	0	2	0	0
T150	0	2	0	0