Unified Coverage Report :: Module :: rv_core_addr_trans

Module : rv_core_addr_trans

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans	100.00	100.00	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36	100.00	92.59			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.27	94.12	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36	100.00	92.59			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.27	94.12	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sel_region	94.88	100.00	86.67			100.00	92.86

Line Coverage for Module : rv_core_addr_trans

	Line No.	Total	Covered	Percent
TOTAL		71	71	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	62	62
45	2	2
46	2	2
51	2	2
76	1	1
83	1	1
84	1	1

---

Cond Coverage for Module : rv_core_addr_trans

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (region_cfg_i[0].en & ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T172,T288,T290
1	1	Covered	T172,T288,T290

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       51
 EXPRESSION (region_cfg_i[1].en & ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T172,T288,T290
1	1	Covered	T172,T288,T290

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (sel_match ? (((addr_i & sel_region.output_mask) | (sel_region.remap_addr & (~sel_region.output_mask)))) : addr_i)
             ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T172,T288,T290

---

Branch Coverage for Module : rv_core_addr_trans

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	76	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	(sel_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T172,T288,T290
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

	Line No.	Total	Covered	Percent
TOTAL		71	71	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	62	62
45	2	2
46	2	2
51	2	2
76	1	1
83	1	1
84	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (region_cfg_i[0].en & ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T172,T288,T290
1	0	Covered	T172,T288,T290
1	1	Covered	T172,T288,T290

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T172,T288,T290

 LINE       51
 EXPRESSION (region_cfg_i[1].en & ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T172,T288,T290
1	0	Covered	T172,T288,T290
1	1	Covered	T172,T288,T290

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T172,T288,T290

 LINE       76
 EXPRESSION (sel_match ? (((addr_i & sel_region.output_mask) | (sel_region.remap_addr & (~sel_region.output_mask)))) : addr_i)
             ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T172,T288,T290

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	76	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	(sel_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T172,T288,T290
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

	Line No.	Total	Covered	Percent
TOTAL		71	71	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	62	62
45	2	2
46	2	2
51	2	2
76	1	1
83	1	1
84	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (region_cfg_i[0].en & ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T172,T288,T290
1	1	Covered	T172,T288,T290

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T17
1	Covered	T4,T5,T6

 LINE       51
 EXPRESSION (region_cfg_i[1].en & ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T172,T288,T290
1	1	Covered	T172,T288,T290

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T17
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (sel_match ? (((addr_i & sel_region.output_mask) | (sel_region.remap_addr & (~sel_region.output_mask)))) : addr_i)
             ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T172,T288,T290

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	76	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	(sel_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T172,T288,T290
0	Covered	T4,T5,T6