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 LINE       36671
 EXPRESSION (addr_hit[561] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T20
1	0	1	Covered	T4,T6,T20
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       36674
 EXPRESSION (addr_hit[562] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T20
1	0	1	Covered	T4,T6,T20
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       36677
 EXPRESSION (addr_hit[563] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T20
1	0	1	Covered	T4,T6,T20
1	1	0	Not Covered
1	1	1	Covered	T14

 LINE       36680
 EXPRESSION (addr_hit[564] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T20
1	0	1	Covered	T4,T6,T20
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T7

 LINE       36683
 EXPRESSION (addr_hit[565] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T20
1	0	1	Covered	T4,T6,T20
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       36686
 EXPRESSION (addr_hit[566] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T20
1	0	1	Covered	T4,T6,T20
1	1	0	Not Covered
1	1	1	Covered	T2

 LINE       36689
 EXPRESSION (addr_hit[567] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T20
1	0	1	Covered	T4,T6,T20
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T126

 LINE       40162
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3