Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.72 95.34 72.08 86.26 93.11 91.82


Total modules in report: 109
modlist.html | modlist1.html
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
prim_mubi4_dec 0.00 0.00
pinmux_wkup 64.07 68.42 69.23 54.55
rv_dm 64.39 64.39
prim_packer_fifo 68.93 100.00 90.00 85.71 0.00
rv_plic_gateway 69.17 100.00 20.00 87.50
padring 76.20 98.18 54.21
ast 78.29 78.29
pinmux 78.35 79.44 80.05 66.10 74.16 92.00
spi_device 79.63 79.63
xbar_main 80.83 80.83
top_earlgrey 82.94 90.68 58.14 100.00
tlul_err 83.23 96.15 74.29 62.50 100.00
usbdev 83.82 83.82
spi_host 84.36 84.36
otp_ctrl 84.41 84.41
entropy_src 84.46 84.46
i2c 84.66 84.66
hmac 84.81 84.81
prim_generic_clock_mux2 85.19 100.00 55.56 100.00
rv_core_ibex 87.48 94.12 89.29 85.81 100.00 68.18
  prim_reg_cdc_arb 88.49 94.00 86.05 73.91 100.00
rv_core_ibex_cfg_reg_top 88.80 98.88 62.06 94.29 100.00
pwm 88.89 88.89
  prim_generic_pad_wrapper 88.89 88.89 83.33 83.33 100.00
  tlul_adapter_host 89.09 91.11 75.79 89.44 100.00
keymgr 89.29 89.29
rv_timer 89.73 89.73
adc_ctrl 89.81 89.81
xbar_peri 89.94 89.94
pattgen 90.00 90.00
aon_timer 90.13 90.13
uart 90.26 90.26
sysrst_ctrl 91.02 91.02
lc_ctrl 91.05 91.05
pinmux_reg_top 91.27 98.45 66.62 100.00 100.00
prim_max_tree 91.56 89.27 76.97 100.00 100.00
  tlul_rsp_intg_gen 91.67 83.33 100.00
prim_sync_reqack 91.67 100.00 66.67 100.00 100.00
tlul_err_resp 91.75 95.24 80.00 100.00
rstmgr 91.79 91.79
sensor_ctrl 91.86 92.79 88.00 78.52 100.00 100.00
chip_earlgrey_asic 91.90 80.00 100.00 95.71
rom_ctrl 92.06 92.06
rv_plic_reg_top 92.38 100.00 70.00 99.52 100.00
tlul_socket_1n 92.60 89.29 86.36 94.74 100.00
pwrmgr 92.64 92.64
sensor_ctrl_reg_top 92.95 100.00 71.82 100.00 100.00
tlul_rsp_intg_chk 93.33 100.00 80.00 100.00
ibex_top 93.58 93.58
flash_ctrl 93.96 93.96
sram_ctrl 93.99 93.99
tlul_adapter_reg 94.24 97.37 79.59 100.00 100.00
gpio 94.44 94.44
clkmgr 94.77 94.77
prim_arbiter_fixed 94.88 100.00 86.67 100.00 92.86
edn 95.62 95.62
rv_plic 96.12 99.83 100.00 90.78 100.00 90.00
prim_edn_req 96.15 100.00 84.62 100.00 100.00
prim_generic_usb_diff_rx 96.30 100.00 88.89 100.00
aes 96.62 96.62
csrng 96.93 96.93
usbdev_aon_wake 96.98 100.00 93.18 94.74 100.00
alert_handler 97.21 97.21
otbn 97.23 97.23
  prim_reg_cdc 97.25 100.00 89.01 100.00 100.00
kmac 98.28 98.28
  prim_subreg_arb 99.60 100.00 98.81 100.00
pinmux_strap_sampling 99.83 99.34 100.00 100.00 100.00
  prim_lc_sync 100.00 100.00 100.00
prim_lc_sender 100.00 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
tlul_cmd_intg_gen 100.00 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
prim_edge_detector 100.00 100.00 100.00 100.00
clk_ctrl_and_main_pd_sva_if 100.00 100.00
  prim_subreg 100.00 100.00 100.00 100.00
prim_filter 100.00 100.00 100.00 100.00
pinmux_jtag_breakout 100.00 100.00 100.00
prim_lc_or_hardened 100.00 100.00 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00 100.00 100.00
prim_pulse_sync 100.00 100.00 100.00 100.00 100.00
prim_fifo_sync 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
prim_esc_receiver 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_sync_reqack_data 100.00 100.00 100.00
rv_core_addr_trans 100.00 100.00 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
rv_plic_target 100.00 100.00 100.00 100.00
prim_mubi4_sync 100.00 100.00
prim_generic_clock_buf 100.00 100.00
pinmux_jtag_buf
prim_usb_diff_rx
prim_clock_buf
tlul_data_integ_enc
prim_reg_we_check