Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1107728	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34137186

1

T4

4609

T5

52866

T6

4868

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	24619105	1			T4	1586		T5	21942		T6	2196
values[0x0]	9517290	1			T4	3023		T5	30924		T6	2672
values[0x1]	1108519	1			T4	198		T5	3265		T6	429

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8378	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35236536

1

T4

4807

T5

56131

T6

5297

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17609646	1			T4	2404		T5	28068		T6	2649
valid_sources[0x01]	17608726	1			T4	2403		T5	28063		T6	2648
valid_sources[0x02]	456	1			T42	37		T43	63		T44	27
valid_sources[0x03]	514	1			T65	2		T66	2		T42	51
valid_sources[0x04]	398	1			T8	1		T42	37		T43	49
valid_sources[0x05]	351	1			T42	36		T43	62		T44	72
valid_sources[0x06]	315	1			T66	1		T42	37		T43	33
valid_sources[0x07]	438	1			T42	37		T43	69		T44	46
valid_sources[0x08]	357	1			T65	2		T42	37		T43	49
valid_sources[0x09]	527	1			T65	1		T42	50		T43	45
valid_sources[0x0a]	379	1			T65	1		T66	1		T42	40
valid_sources[0x0b]	341	1			T66	1		T42	34		T43	47
valid_sources[0x0c]	367	1			T139	39		T42	37		T43	44
valid_sources[0x0d]	507	1			T65	2		T42	47		T43	51
valid_sources[0x0e]	375	1			T8	1		T65	1		T66	1
valid_sources[0x0f]	398	1			T8	1		T66	1		T42	50
valid_sources[0x10]	393	1			T42	38		T43	67		T44	90
valid_sources[0x11]	348	1			T66	1		T42	29		T43	55
valid_sources[0x12]	355	1			T42	49		T43	59		T44	55
valid_sources[0x13]	339	1			T42	57		T43	47		T44	57
valid_sources[0x14]	372	1			T66	1		T42	30		T43	63
valid_sources[0x15]	414	1			T8	1		T65	1		T66	2
valid_sources[0x16]	434	1			T8	1		T65	2		T42	41
valid_sources[0x17]	440	1			T8	1		T66	1		T42	36
valid_sources[0x18]	367	1			T8	2		T66	2		T42	43
valid_sources[0x19]	390	1			T8	1		T65	3		T42	43
valid_sources[0x1a]	336	1			T66	1		T42	42		T43	39
valid_sources[0x1b]	405	1			T66	1		T42	50		T43	61
valid_sources[0x1c]	412	1			T8	1		T65	3		T42	48
valid_sources[0x1d]	357	1			T8	1		T65	1		T42	36
valid_sources[0x1e]	407	1			T8	1		T42	47		T43	41
valid_sources[0x1f]	304	1			T8	1		T65	1		T42	52
valid_sources[0x20]	320	1			T8	1		T66	2		T42	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24619105

1

T4

1586

T5

21942

T6

2196

values[0x0]

all_enables

biggest_size

9512981

1

T4

3023

T5

30924

T6

2672

values[0x1]

all_enables

biggest_size

5100

1

T8

22

T65

23

T66

22