| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 40.86 |
40.86 |
44.87 |
44.87 |
42.99 |
42.99 |
32.77 |
32.77 |
|
|
58.02 |
58.02 |
59.27 |
59.27 |
7.24 |
7.24 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3251759556 |
| 51.96 |
11.10 |
53.47 |
8.59 |
52.34 |
9.35 |
38.44 |
5.67 |
|
|
66.45 |
8.43 |
85.49 |
26.22 |
15.57 |
8.33 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1471579997 |
| 60.20 |
8.24 |
53.51 |
0.04 |
52.39 |
0.05 |
41.29 |
2.85 |
|
|
66.46 |
0.01 |
85.49 |
0.00 |
62.06 |
46.49 |
/workspace/coverage/default/0.chip_sw_alert_test.1726761358 |
| 65.79 |
5.59 |
65.01 |
11.50 |
58.36 |
5.97 |
45.66 |
4.37 |
|
|
69.78 |
3.32 |
89.69 |
4.20 |
66.23 |
4.17 |
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4066699694 |
| 70.65 |
4.86 |
76.32 |
11.31 |
65.68 |
7.32 |
46.07 |
0.41 |
|
|
79.89 |
10.12 |
89.69 |
0.00 |
66.23 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.1569029088 |
| 73.36 |
2.72 |
76.32 |
0.00 |
65.68 |
0.00 |
62.37 |
16.31 |
|
|
79.89 |
0.00 |
89.69 |
0.00 |
66.23 |
0.00 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1250860624 |
| 75.54 |
2.18 |
78.41 |
2.09 |
68.32 |
2.64 |
68.49 |
6.12 |
|
|
81.75 |
1.86 |
90.03 |
0.35 |
66.23 |
0.00 |
/workspace/coverage/default/2.rom_e2e_static_critical.3838790089 |
| 77.48 |
1.94 |
81.93 |
3.52 |
72.21 |
3.89 |
68.92 |
0.43 |
|
|
85.56 |
3.81 |
90.03 |
0.00 |
66.23 |
0.00 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2684939953 |
| 78.91 |
1.43 |
82.21 |
0.29 |
72.36 |
0.16 |
76.51 |
7.59 |
|
|
85.74 |
0.18 |
90.38 |
0.35 |
66.23 |
0.00 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2969274750 |
| 80.27 |
1.36 |
84.62 |
2.41 |
74.43 |
2.07 |
77.83 |
1.33 |
|
|
88.12 |
2.39 |
90.38 |
0.00 |
66.23 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.435954772 |
| 81.36 |
1.09 |
86.23 |
1.61 |
76.88 |
2.45 |
78.06 |
0.23 |
|
|
90.39 |
2.27 |
90.38 |
0.00 |
66.23 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3327721058 |
| 82.25 |
0.89 |
86.70 |
0.46 |
77.06 |
0.18 |
78.68 |
0.62 |
|
|
90.62 |
0.23 |
94.23 |
3.85 |
66.23 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3924768253 |
| 82.95 |
0.70 |
87.46 |
0.76 |
77.78 |
0.72 |
80.40 |
1.73 |
|
|
91.42 |
0.80 |
94.41 |
0.17 |
66.23 |
0.00 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2114089042 |
| 83.59 |
0.64 |
88.30 |
0.84 |
78.62 |
0.84 |
81.08 |
0.68 |
|
|
92.04 |
0.62 |
94.41 |
0.00 |
67.11 |
0.88 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2540764307 |
| 84.03 |
0.44 |
88.63 |
0.33 |
80.09 |
1.47 |
81.12 |
0.04 |
|
|
92.82 |
0.78 |
94.41 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/0.chip_jtag_csr_rw.1534097013 |
| 84.44 |
0.41 |
89.20 |
0.57 |
80.58 |
0.48 |
82.04 |
0.92 |
|
|
93.31 |
0.49 |
94.41 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2419779513 |
| 84.83 |
0.39 |
89.98 |
0.78 |
81.18 |
0.60 |
82.57 |
0.53 |
|
|
93.74 |
0.44 |
94.41 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/1.chip_sw_gpio.114533167 |
| 85.15 |
0.32 |
90.42 |
0.44 |
81.53 |
0.35 |
82.83 |
0.26 |
|
|
94.10 |
0.36 |
94.93 |
0.52 |
67.11 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3713499735 |
| 85.45 |
0.30 |
90.45 |
0.03 |
81.55 |
0.02 |
82.84 |
0.01 |
|
|
94.13 |
0.02 |
95.10 |
0.17 |
68.64 |
1.54 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3809009481 |
| 85.72 |
0.27 |
90.71 |
0.27 |
81.62 |
0.07 |
83.22 |
0.38 |
|
|
94.13 |
0.01 |
95.98 |
0.87 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3108962072 |
| 85.92 |
0.21 |
90.71 |
0.00 |
81.62 |
0.00 |
84.46 |
1.24 |
|
|
94.13 |
0.00 |
95.98 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2774203117 |
| 86.12 |
0.19 |
90.89 |
0.17 |
81.72 |
0.10 |
84.91 |
0.44 |
|
|
94.23 |
0.10 |
96.33 |
0.35 |
68.64 |
0.00 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.49376836 |
| 86.27 |
0.15 |
90.89 |
0.01 |
81.73 |
0.01 |
85.76 |
0.86 |
|
|
94.24 |
0.01 |
96.33 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2773844694 |
| 86.40 |
0.14 |
91.10 |
0.21 |
81.85 |
0.12 |
85.95 |
0.19 |
|
|
94.33 |
0.09 |
96.33 |
0.00 |
68.86 |
0.22 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1943029585 |
| 86.54 |
0.13 |
91.35 |
0.25 |
82.12 |
0.26 |
86.24 |
0.29 |
|
|
94.33 |
0.00 |
96.33 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1247367138 |
| 86.64 |
0.11 |
91.35 |
0.00 |
82.12 |
0.00 |
86.88 |
0.65 |
|
|
94.33 |
0.00 |
96.33 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1552814656 |
| 86.75 |
0.11 |
91.38 |
0.03 |
82.26 |
0.14 |
86.90 |
0.02 |
|
|
94.38 |
0.05 |
96.50 |
0.17 |
69.08 |
0.22 |
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.597227360 |
| 86.84 |
0.09 |
91.38 |
0.01 |
82.27 |
0.01 |
87.43 |
0.52 |
|
|
94.39 |
0.01 |
96.50 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.425665774 |
| 86.93 |
0.09 |
91.68 |
0.30 |
82.31 |
0.04 |
87.61 |
0.19 |
|
|
94.39 |
0.01 |
96.50 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1448045275 |
| 87.01 |
0.08 |
91.68 |
0.01 |
82.53 |
0.22 |
87.61 |
0.00 |
|
|
94.64 |
0.24 |
96.50 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4284405972 |
| 87.08 |
0.08 |
91.69 |
0.01 |
82.54 |
0.02 |
87.87 |
0.25 |
|
|
94.64 |
0.00 |
96.68 |
0.17 |
69.08 |
0.00 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2873348622 |
| 87.16 |
0.07 |
91.70 |
0.01 |
82.56 |
0.02 |
87.87 |
0.00 |
|
|
94.66 |
0.02 |
96.85 |
0.17 |
69.30 |
0.22 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.1006301718 |
| 87.23 |
0.07 |
91.70 |
0.01 |
82.59 |
0.02 |
87.87 |
0.00 |
|
|
94.67 |
0.01 |
97.03 |
0.17 |
69.52 |
0.22 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.2700936666 |
| 87.30 |
0.07 |
91.71 |
0.01 |
82.60 |
0.01 |
87.87 |
0.01 |
|
|
94.68 |
0.01 |
97.20 |
0.17 |
69.74 |
0.22 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1704543789 |
| 87.37 |
0.07 |
91.71 |
0.01 |
82.61 |
0.01 |
87.88 |
0.01 |
|
|
94.69 |
0.01 |
97.38 |
0.17 |
69.96 |
0.22 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.288974812 |
| 87.44 |
0.07 |
91.71 |
0.00 |
82.61 |
0.00 |
88.30 |
0.42 |
|
|
94.69 |
0.00 |
97.38 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1005663569 |
| 87.48 |
0.04 |
91.71 |
0.00 |
82.72 |
0.12 |
88.32 |
0.02 |
|
|
94.82 |
0.13 |
97.38 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3684825549 |
| 87.53 |
0.04 |
91.71 |
0.00 |
82.72 |
0.00 |
88.37 |
0.04 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
70.18 |
0.22 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3975154586 |
| 87.57 |
0.04 |
91.71 |
0.00 |
82.72 |
0.00 |
88.62 |
0.25 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
70.18 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2482429818 |
| 87.61 |
0.04 |
91.71 |
0.00 |
82.72 |
0.00 |
88.63 |
0.02 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
70.39 |
0.22 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2216967694 |
| 87.65 |
0.04 |
91.71 |
0.00 |
82.73 |
0.01 |
88.64 |
0.01 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
70.61 |
0.22 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2120255884 |
| 87.69 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.66 |
0.01 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
70.83 |
0.22 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.776389839 |
| 87.72 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.88 |
0.23 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
70.83 |
0.00 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3247226421 |
| 87.76 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.89 |
0.01 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
71.05 |
0.22 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2703088465 |
| 87.80 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.89 |
0.01 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
71.27 |
0.22 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1401371611 |
| 87.84 |
0.04 |
91.71 |
0.00 |
82.73 |
0.01 |
88.89 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
71.49 |
0.22 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.4280283967 |
| 87.87 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.01 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
71.71 |
0.22 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3584437241 |
| 87.91 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
71.93 |
0.22 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2482284067 |
| 87.95 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
72.15 |
0.22 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.1215307592 |
| 87.98 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
72.37 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1738951651 |
| 88.02 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
72.59 |
0.22 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1579885268 |
| 88.06 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
72.81 |
0.22 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.1552767456 |
| 88.09 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
73.03 |
0.22 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1317153011 |
| 88.13 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
73.25 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.3956764074 |
| 88.17 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
73.46 |
0.22 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.1704921768 |
| 88.20 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
73.68 |
0.22 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.68643721 |
| 88.24 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
73.90 |
0.22 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.436469144 |
| 88.28 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
74.12 |
0.22 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2885851172 |
| 88.31 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
74.34 |
0.22 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.1046934779 |
| 88.35 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
74.56 |
0.22 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.701259337 |
| 88.39 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
74.78 |
0.22 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1154798645 |
| 88.42 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
75.00 |
0.22 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.166841359 |
| 88.46 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
75.22 |
0.22 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.3626777578 |
| 88.49 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
75.44 |
0.22 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.4044738432 |
| 88.53 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
75.66 |
0.22 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.684674019 |
| 88.57 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
75.88 |
0.22 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.2989379142 |
| 88.60 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
76.10 |
0.22 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.1940355491 |
| 88.64 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
76.32 |
0.22 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.4145871757 |
| 88.68 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
76.54 |
0.22 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.47388903 |
| 88.71 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
76.75 |
0.22 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3405693312 |
| 88.75 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
76.97 |
0.22 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.144716226 |
| 88.79 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
77.19 |
0.22 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2753054620 |
| 88.82 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
77.41 |
0.22 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.3792886256 |
| 88.86 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
77.63 |
0.22 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.937611280 |
| 88.90 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
77.85 |
0.22 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3898861249 |
| 88.93 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
78.07 |
0.22 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.4057638282 |
| 88.97 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
78.29 |
0.22 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.231970867 |
| 89.01 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
78.51 |
0.22 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1544604255 |
| 89.04 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
78.73 |
0.22 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.810249061 |
| 89.08 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
78.95 |
0.22 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2872910719 |
| 89.12 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
79.17 |
0.22 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.4220679647 |
| 89.15 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
79.39 |
0.22 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3229507845 |
| 89.19 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
79.61 |
0.22 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.284149979 |
| 89.23 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
79.82 |
0.22 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2828170871 |
| 89.26 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
80.04 |
0.22 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1512985943 |
| 89.30 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
80.26 |
0.22 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.4020393940 |
| 89.34 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
80.48 |
0.22 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1972395545 |
| 89.37 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
80.70 |
0.22 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2137658545 |
| 89.41 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
80.92 |
0.22 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.450266576 |
| 89.45 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
81.14 |
0.22 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2214655358 |
| 89.48 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
81.36 |
0.22 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1799959420 |
| 89.52 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
81.58 |
0.22 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3282742951 |
| 89.55 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
81.80 |
0.22 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3961796291 |
| 89.59 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
82.02 |
0.22 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2824696120 |
| 89.63 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
82.24 |
0.22 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.295070579 |
| 89.66 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
82.46 |
0.22 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1791130947 |
| 89.70 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
82.68 |
0.22 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2098727524 |
| 89.74 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
82.89 |
0.22 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.1058110307 |
| 89.77 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
83.11 |
0.22 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.4094358320 |
| 89.81 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
83.33 |
0.22 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.183573492 |
| 89.85 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
83.55 |
0.22 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2455813937 |
| 89.88 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
83.77 |
0.22 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2188975323 |
| 89.92 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
83.99 |
0.22 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2818990133 |
| 89.96 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
84.21 |
0.22 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2300242852 |
| 89.99 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
84.43 |
0.22 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.757379170 |
| 90.03 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
84.65 |
0.22 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2504586768 |
| 90.07 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
84.87 |
0.22 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2350969149 |
| 90.10 |
0.04 |
91.71 |
0.00 |
82.73 |
0.00 |
88.90 |
0.00 |
|
|
94.82 |
0.00 |
97.38 |
0.00 |
85.09 |
0.22 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1756066644 |
| 90.13 |
0.03 |
91.76 |
0.05 |
82.83 |
0.10 |
88.90 |
0.00 |
|
|
94.85 |
0.03 |
97.38 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3048060187 |
| 90.16 |
0.03 |
91.76 |
0.00 |
82.83 |
0.00 |
88.90 |
0.01 |
|
|
94.85 |
0.00 |
97.55 |
0.17 |
85.09 |
0.00 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1407795817 |
| 90.19 |
0.03 |
91.76 |
0.00 |
82.83 |
0.00 |
89.06 |
0.17 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3198405376 |
| 90.22 |
0.03 |
91.82 |
0.06 |
82.87 |
0.05 |
89.07 |
0.01 |
|
|
94.90 |
0.06 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.2124075486 |
| 90.24 |
0.03 |
91.82 |
0.00 |
82.87 |
0.00 |
89.23 |
0.16 |
|
|
94.90 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3320437383 |
| 90.27 |
0.03 |
91.89 |
0.07 |
82.90 |
0.03 |
89.25 |
0.01 |
|
|
94.95 |
0.05 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.14975343 |
| 90.30 |
0.03 |
91.96 |
0.07 |
82.90 |
0.00 |
89.33 |
0.08 |
|
|
94.96 |
0.01 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.2360059344 |
| 90.32 |
0.02 |
91.96 |
0.00 |
83.05 |
0.15 |
89.33 |
0.00 |
|
|
94.96 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.3609941709 |
| 90.35 |
0.02 |
91.96 |
0.01 |
83.07 |
0.02 |
89.44 |
0.11 |
|
|
94.96 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1836582526 |
| 90.37 |
0.02 |
92.02 |
0.06 |
83.12 |
0.05 |
89.45 |
0.01 |
|
|
94.99 |
0.02 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2337670902 |
| 90.39 |
0.02 |
92.13 |
0.11 |
83.13 |
0.01 |
89.45 |
0.01 |
|
|
94.99 |
0.01 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1271037233 |
| 90.41 |
0.02 |
92.14 |
0.01 |
83.14 |
0.02 |
89.52 |
0.07 |
|
|
95.01 |
0.02 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.242556926 |
| 90.43 |
0.02 |
92.14 |
0.00 |
83.14 |
0.00 |
89.63 |
0.11 |
|
|
95.01 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2685607488 |
| 90.44 |
0.01 |
92.19 |
0.05 |
83.15 |
0.01 |
89.64 |
0.01 |
|
|
95.03 |
0.02 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1574858830 |
| 90.45 |
0.01 |
92.26 |
0.07 |
83.16 |
0.01 |
89.64 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3490969364 |
| 90.46 |
0.01 |
92.26 |
0.00 |
83.23 |
0.07 |
89.64 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3843346208 |
| 90.47 |
0.01 |
92.26 |
0.00 |
83.28 |
0.06 |
89.64 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.2427429636 |
| 90.48 |
0.01 |
92.26 |
0.00 |
83.33 |
0.05 |
89.64 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.2198372928 |
| 90.49 |
0.01 |
92.26 |
0.00 |
83.33 |
0.00 |
89.68 |
0.05 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1315280773 |
| 90.50 |
0.01 |
92.26 |
0.00 |
83.33 |
0.00 |
89.72 |
0.04 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3804747957 |
| 90.50 |
0.01 |
92.29 |
0.03 |
83.34 |
0.01 |
89.72 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.18779288 |
| 90.51 |
0.01 |
92.29 |
0.00 |
83.34 |
0.00 |
89.76 |
0.04 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3394413767 |
| 90.52 |
0.01 |
92.29 |
0.00 |
83.34 |
0.00 |
89.80 |
0.04 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_jtag_mem_access.378102765 |
| 90.52 |
0.01 |
92.30 |
0.01 |
83.36 |
0.02 |
89.81 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.498451935 |
| 90.53 |
0.01 |
92.30 |
0.00 |
83.36 |
0.00 |
89.83 |
0.03 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3755363601 |
| 90.53 |
0.01 |
92.30 |
0.00 |
83.36 |
0.00 |
89.86 |
0.03 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1878696760 |
| 90.53 |
0.01 |
92.30 |
0.00 |
83.36 |
0.01 |
89.88 |
0.01 |
|
|
95.03 |
0.01 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.880188400 |
| 90.54 |
0.01 |
92.30 |
0.00 |
83.38 |
0.02 |
89.88 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.3760915694 |
| 90.54 |
0.01 |
92.30 |
0.00 |
83.39 |
0.01 |
89.89 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1873260236 |
| 90.55 |
0.01 |
92.30 |
0.01 |
83.41 |
0.01 |
89.90 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4123030126 |
| 90.55 |
0.01 |
92.31 |
0.01 |
83.42 |
0.01 |
89.90 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.696795438 |
| 90.55 |
0.01 |
92.31 |
0.00 |
83.44 |
0.02 |
89.90 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1900211262 |
| 90.56 |
0.01 |
92.31 |
0.00 |
83.44 |
0.00 |
89.92 |
0.02 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1453672057 |
| 90.56 |
0.01 |
92.31 |
0.00 |
83.45 |
0.01 |
89.94 |
0.02 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1691729741 |
| 90.56 |
0.01 |
92.31 |
0.00 |
83.45 |
0.00 |
89.95 |
0.02 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.3624694110 |
| 90.57 |
0.01 |
92.31 |
0.00 |
83.45 |
0.00 |
89.97 |
0.02 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.1110629005 |
| 90.57 |
0.01 |
92.31 |
0.00 |
83.47 |
0.02 |
89.97 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio.230129698 |
| 90.57 |
0.01 |
92.31 |
0.01 |
83.47 |
0.01 |
89.98 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1574734945 |
| 90.57 |
0.01 |
92.32 |
0.01 |
83.47 |
0.01 |
89.98 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.1444022120 |
| 90.58 |
0.01 |
92.32 |
0.00 |
83.47 |
0.00 |
90.00 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1987846938 |
| 90.58 |
0.01 |
92.32 |
0.00 |
83.47 |
0.00 |
90.01 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4080941886 |
| 90.58 |
0.01 |
92.33 |
0.01 |
83.47 |
0.00 |
90.01 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3185277526 |
| 90.58 |
0.01 |
92.33 |
0.01 |
83.47 |
0.00 |
90.02 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1009945750 |
| 90.58 |
0.01 |
92.33 |
0.00 |
83.48 |
0.01 |
90.02 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.4155896958 |
| 90.59 |
0.01 |
92.33 |
0.00 |
83.49 |
0.01 |
90.02 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4010101024 |
| 90.59 |
0.01 |
92.33 |
0.00 |
83.50 |
0.01 |
90.02 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3197203609 |
| 90.59 |
0.01 |
92.33 |
0.00 |
83.51 |
0.01 |
90.02 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.13916305 |
| 90.59 |
0.01 |
92.34 |
0.01 |
83.51 |
0.00 |
90.02 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_tap_straps_rma.40093658 |
| 90.59 |
0.01 |
92.34 |
0.00 |
83.51 |
0.00 |
90.03 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.711912574 |
| 90.59 |
0.01 |
92.34 |
0.00 |
83.51 |
0.00 |
90.04 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1785033003 |
| 90.60 |
0.01 |
92.34 |
0.00 |
83.51 |
0.00 |
90.05 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2669131432 |
| 90.60 |
0.01 |
92.34 |
0.00 |
83.51 |
0.00 |
90.06 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2645187676 |
| 90.60 |
0.01 |
92.34 |
0.00 |
83.51 |
0.00 |
90.07 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2879896338 |
| 90.60 |
0.01 |
92.34 |
0.00 |
83.52 |
0.01 |
90.08 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1879494195 |
| 90.60 |
0.01 |
92.34 |
0.00 |
83.53 |
0.01 |
90.08 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3337218761 |
| 90.60 |
0.01 |
92.34 |
0.00 |
83.53 |
0.01 |
90.08 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_gpio.4077679244 |
| 90.60 |
0.01 |
92.34 |
0.00 |
83.54 |
0.01 |
90.08 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.495370928 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.54 |
0.00 |
90.08 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2932647737 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.54 |
0.00 |
90.09 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2429981567 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.54 |
0.01 |
90.09 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.2992689973 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.54 |
0.00 |
90.10 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3890318999 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.54 |
0.00 |
90.10 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4031382057 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.54 |
0.00 |
90.11 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1802628029 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.54 |
0.00 |
90.11 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.968223605 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.54 |
0.00 |
90.12 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1316383958 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.54 |
0.00 |
90.12 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.707643579 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.54 |
0.00 |
90.13 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1603705660 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.55 |
0.01 |
90.13 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1078129802 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.55 |
0.01 |
90.13 |
0.00 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3976929150 |
| 90.61 |
0.01 |
92.34 |
0.00 |
83.55 |
0.00 |
90.13 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.818236125 |
| 90.62 |
0.01 |
92.34 |
0.00 |
83.55 |
0.00 |
90.13 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.251234138 |
| 90.62 |
0.01 |
92.34 |
0.00 |
83.55 |
0.00 |
90.13 |
0.01 |
|
|
95.03 |
0.00 |
97.55 |
0.00 |
85.09 |
0.00 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2083572043 |
| Name |
| /workspace/coverage/default/0.chip_sival_flash_info_access.1077120143 |
| /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3928514402 |
| /workspace/coverage/default/0.chip_sw_aes_enc.320303713 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2012468346 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3723983184 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.139266801 |
| /workspace/coverage/default/0.chip_sw_aes_idle.1257720047 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.3087170052 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.2675675480 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1900750518 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3145840775 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1864612364 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2465036398 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1720787083 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.469232055 |
| /workspace/coverage/default/0.chip_sw_aon_timer_irq.1069474976 |
| /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2329887674 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.688024356 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2450274438 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.445524339 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1104194841 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3994025945 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3423283143 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2795322436 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.791029883 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3876119697 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1410643536 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.868412384 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3859225318 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1232978378 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.239945420 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3479599338 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2597274676 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.659804814 |
| /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3855189908 |
| /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.467405238 |
| /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.594688535 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3377624760 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.384836347 |
| /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1290903572 |
| /workspace/coverage/default/0.chip_sw_csrng_kat_test.3338232220 |
| /workspace/coverage/default/0.chip_sw_csrng_smoketest.3098615760 |
| /workspace/coverage/default/0.chip_sw_data_integrity_escalation.153788011 |
| /workspace/coverage/default/0.chip_sw_edn_auto_mode.2874517902 |
| /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1991186871 |
| /workspace/coverage/default/0.chip_sw_edn_kat.425640707 |
| /workspace/coverage/default/0.chip_sw_edn_sw_mode.2848380543 |
| /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1238260467 |
| /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2305339326 |
| /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2943716288 |
| /workspace/coverage/default/0.chip_sw_example_concurrency.3714603604 |
| /workspace/coverage/default/0.chip_sw_example_flash.1393985852 |
| /workspace/coverage/default/0.chip_sw_example_manufacturer.2668868113 |
| /workspace/coverage/default/0.chip_sw_example_rom.2629593659 |
| /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.371958480 |
| /workspace/coverage/default/0.chip_sw_flash_crash_alert.735865497 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1253356293 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2835616013 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.326347921 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3874743309 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.902282285 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.756932184 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2535480863 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2375349817 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4116182657 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2698759058 |
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| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2800776392 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4260665187 |
| /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1317729585 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.247319262 |
| /workspace/coverage/default/81.chip_sw_all_escalation_resets.3842888066 |
| /workspace/coverage/default/82.chip_sw_all_escalation_resets.1573513146 |
| /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.533430830 |
| /workspace/coverage/default/83.chip_sw_all_escalation_resets.1272416524 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.42231970 |
| /workspace/coverage/default/84.chip_sw_all_escalation_resets.2236434923 |
| /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2293485940 |
| /workspace/coverage/default/85.chip_sw_all_escalation_resets.2264058152 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3919046921 |
| /workspace/coverage/default/86.chip_sw_all_escalation_resets.4028088932 |
| /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.676798868 |
| /workspace/coverage/default/87.chip_sw_all_escalation_resets.3084522268 |
| /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2986781391 |
| /workspace/coverage/default/88.chip_sw_all_escalation_resets.3120246877 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.727205693 |
| /workspace/coverage/default/89.chip_sw_all_escalation_resets.2743871631 |
| /workspace/coverage/default/9.chip_sw_all_escalation_resets.3610958375 |
| /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2142339583 |
| /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1574899204 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3208942688 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.2677946522 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.3910843615 |
| /workspace/coverage/default/94.chip_sw_all_escalation_resets.427118512 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.2165843734 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.2350468803 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.4286659077 |
| /workspace/coverage/default/98.chip_sw_all_escalation_resets.1884623813 |
| /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3169391619 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3405577174 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3000455513 |
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.818009604 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4062238017 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1949507792 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1346772604 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4087241997 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T4 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2229763188 |
|
|
Jul 01 07:12:28 PM PDT 24 |
Jul 01 07:16:48 PM PDT 24 |
3245252644 ps |
| T5 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3251759556 |
|
|
Jul 01 07:11:00 PM PDT 24 |
Jul 01 07:55:01 PM PDT 24 |
25055683906 ps |
| T6 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3924768253 |
|
|
Jul 01 07:14:35 PM PDT 24 |
Jul 01 07:18:40 PM PDT 24 |
2809924432 ps |
| T31 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.242556926 |
|
|
Jul 01 07:11:33 PM PDT 24 |
Jul 01 09:08:26 PM PDT 24 |
32228199360 ps |
| T17 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1943029585 |
|
|
Jul 01 07:46:11 PM PDT 24 |
Jul 01 07:57:03 PM PDT 24 |
5133299672 ps |
| T18 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1836582526 |
|
|
Jul 01 07:38:19 PM PDT 24 |
Jul 01 07:56:35 PM PDT 24 |
8727975240 ps |
| T19 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1259344502 |
|
|
Jul 01 07:20:50 PM PDT 24 |
Jul 01 07:35:22 PM PDT 24 |
8857737296 ps |
| T165 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.594688535 |
|
|
Jul 01 07:13:49 PM PDT 24 |
Jul 01 07:16:34 PM PDT 24 |
2234836940 ps |
| T114 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3975154586 |
|
|
Jul 01 07:41:55 PM PDT 24 |
Jul 01 07:56:34 PM PDT 24 |
6137242148 ps |
| T142 |
/workspace/coverage/default/2.chip_sw_aes_idle.1883738359 |
|
|
Jul 01 07:30:40 PM PDT 24 |
Jul 01 07:35:52 PM PDT 24 |
2777564992 ps |
| T57 |
/workspace/coverage/default/2.rom_e2e_static_critical.3838790089 |
|
|
Jul 01 07:40:29 PM PDT 24 |
Jul 01 08:44:18 PM PDT 24 |
17093342238 ps |
| T136 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3747623046 |
|
|
Jul 01 07:19:18 PM PDT 24 |
Jul 01 07:44:35 PM PDT 24 |
7244748150 ps |
| T20 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2487088434 |
|
|
Jul 01 07:18:53 PM PDT 24 |
Jul 01 08:50:42 PM PDT 24 |
23765109712 ps |
| T62 |
/workspace/coverage/default/1.chip_tap_straps_prod.2565275425 |
|
|
Jul 01 07:24:15 PM PDT 24 |
Jul 01 07:27:25 PM PDT 24 |
2864978917 ps |
| T189 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1735801177 |
|
|
Jul 01 07:30:51 PM PDT 24 |
Jul 01 07:55:14 PM PDT 24 |
6932915246 ps |
| T1 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3713499735 |
|
|
Jul 01 07:25:42 PM PDT 24 |
Jul 01 07:32:57 PM PDT 24 |
7310178350 ps |
| T179 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.567092940 |
|
|
Jul 01 07:24:35 PM PDT 24 |
Jul 01 07:29:24 PM PDT 24 |
2313558066 ps |
| T59 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2829618170 |
|
|
Jul 01 07:24:21 PM PDT 24 |
Jul 01 07:32:14 PM PDT 24 |
4280547268 ps |
| T107 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2465036398 |
|
|
Jul 01 07:11:48 PM PDT 24 |
Jul 01 07:45:04 PM PDT 24 |
6582820232 ps |
| T34 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.49376836 |
|
|
Jul 01 07:20:38 PM PDT 24 |
Jul 01 07:52:06 PM PDT 24 |
24009762240 ps |
| T180 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.419188363 |
|
|
Jul 01 07:19:51 PM PDT 24 |
Jul 01 07:24:17 PM PDT 24 |
3218487260 ps |
| T181 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.776389839 |
|
|
Jul 01 07:42:59 PM PDT 24 |
Jul 01 07:50:15 PM PDT 24 |
4351173004 ps |
| T21 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3268784731 |
|
|
Jul 01 07:32:08 PM PDT 24 |
Jul 01 07:53:19 PM PDT 24 |
7728785449 ps |
| T100 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3596890072 |
|
|
Jul 01 07:39:59 PM PDT 24 |
Jul 01 08:00:36 PM PDT 24 |
8210517772 ps |
| T137 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2596633472 |
|
|
Jul 01 07:09:39 PM PDT 24 |
Jul 01 07:33:35 PM PDT 24 |
8871120626 ps |
| T190 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2703088465 |
|
|
Jul 01 07:41:25 PM PDT 24 |
Jul 01 07:48:40 PM PDT 24 |
3608510608 ps |
| T290 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.3513780668 |
|
|
Jul 01 07:24:22 PM PDT 24 |
Jul 01 07:32:45 PM PDT 24 |
3661915936 ps |
| T287 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.3896115028 |
|
|
Jul 01 07:19:40 PM PDT 24 |
Jul 01 07:25:11 PM PDT 24 |
2712663710 ps |
| T82 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3633722199 |
|
|
Jul 01 07:31:53 PM PDT 24 |
Jul 01 07:48:31 PM PDT 24 |
5647167420 ps |
| T238 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.738941404 |
|
|
Jul 01 07:23:17 PM PDT 24 |
Jul 01 08:35:42 PM PDT 24 |
40473636905 ps |
| T49 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.679620005 |
|
|
Jul 01 07:29:34 PM PDT 24 |
Jul 01 07:37:59 PM PDT 24 |
6122770748 ps |
| T127 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.3752373659 |
|
|
Jul 01 07:34:40 PM PDT 24 |
Jul 01 07:46:14 PM PDT 24 |
4927051448 ps |
| T361 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.4062769825 |
|
|
Jul 01 07:42:51 PM PDT 24 |
Jul 01 07:53:00 PM PDT 24 |
4694106904 ps |
| T522 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1721122807 |
|
|
Jul 01 07:25:41 PM PDT 24 |
Jul 01 07:36:52 PM PDT 24 |
4646431368 ps |
| T60 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2969274750 |
|
|
Jul 01 07:16:16 PM PDT 24 |
Jul 01 07:35:57 PM PDT 24 |
9683381264 ps |
| T28 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3202520008 |
|
|
Jul 01 07:11:04 PM PDT 24 |
Jul 01 07:23:16 PM PDT 24 |
4280337552 ps |
| T405 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3855189908 |
|
|
Jul 01 07:12:15 PM PDT 24 |
Jul 01 07:19:40 PM PDT 24 |
3288686838 ps |
| T128 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2120255884 |
|
|
Jul 01 07:42:33 PM PDT 24 |
Jul 01 07:53:38 PM PDT 24 |
5949016280 ps |
| T268 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.642477944 |
|
|
Jul 01 07:36:33 PM PDT 24 |
Jul 01 07:46:01 PM PDT 24 |
4084594770 ps |
| T332 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.705722886 |
|
|
Jul 01 07:24:35 PM PDT 24 |
Jul 01 07:48:11 PM PDT 24 |
8048923264 ps |
| T406 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.2122351559 |
|
|
Jul 01 07:32:57 PM PDT 24 |
Jul 01 07:47:45 PM PDT 24 |
7237475208 ps |
| T396 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.725326237 |
|
|
Jul 01 07:33:45 PM PDT 24 |
Jul 01 07:39:33 PM PDT 24 |
2941845304 ps |
| T523 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.3751243970 |
|
|
Jul 01 07:26:34 PM PDT 24 |
Jul 01 07:29:41 PM PDT 24 |
2493097120 ps |
| T72 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2114089042 |
|
|
Jul 01 07:28:15 PM PDT 24 |
Jul 01 08:11:59 PM PDT 24 |
19544856165 ps |
| T115 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1434237170 |
|
|
Jul 01 07:39:08 PM PDT 24 |
Jul 01 07:51:41 PM PDT 24 |
5630630736 ps |
| T108 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.3437745451 |
|
|
Jul 01 07:40:59 PM PDT 24 |
Jul 01 07:52:22 PM PDT 24 |
5040252750 ps |
| T58 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.3636386193 |
|
|
Jul 01 07:29:11 PM PDT 24 |
Jul 01 08:29:48 PM PDT 24 |
15116780710 ps |
| T67 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1510641881 |
|
|
Jul 01 07:29:21 PM PDT 24 |
Jul 01 07:39:37 PM PDT 24 |
3646562912 ps |
| T138 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1005663569 |
|
|
Jul 01 07:27:24 PM PDT 24 |
Jul 01 07:35:50 PM PDT 24 |
4174649130 ps |
| T322 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3811118118 |
|
|
Jul 01 07:27:03 PM PDT 24 |
Jul 01 07:39:38 PM PDT 24 |
4917415388 ps |
| T323 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.4286659077 |
|
|
Jul 01 07:47:29 PM PDT 24 |
Jul 01 07:58:11 PM PDT 24 |
5791245000 ps |
| T83 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.3648592065 |
|
|
Jul 01 07:29:29 PM PDT 24 |
Jul 01 07:48:15 PM PDT 24 |
5962431176 ps |
| T324 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3584437241 |
|
|
Jul 01 07:45:40 PM PDT 24 |
Jul 01 07:56:46 PM PDT 24 |
6174681920 ps |
| T143 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2773844694 |
|
|
Jul 01 07:14:14 PM PDT 24 |
Jul 01 07:38:34 PM PDT 24 |
6538434760 ps |
| T524 |
/workspace/coverage/default/2.chip_sw_example_concurrency.2532370002 |
|
|
Jul 01 07:27:03 PM PDT 24 |
Jul 01 07:31:48 PM PDT 24 |
3575525992 ps |
| T134 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1250860624 |
|
|
Jul 01 07:28:15 PM PDT 24 |
Jul 01 07:48:10 PM PDT 24 |
6492155090 ps |
| T131 |
/workspace/coverage/default/2.chip_sw_hmac_enc.1020555098 |
|
|
Jul 01 07:32:16 PM PDT 24 |
Jul 01 07:37:58 PM PDT 24 |
2958391944 ps |
| T61 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.880188400 |
|
|
Jul 01 07:36:01 PM PDT 24 |
Jul 01 07:47:25 PM PDT 24 |
5361819524 ps |
| T415 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.938171030 |
|
|
Jul 01 07:30:34 PM PDT 24 |
Jul 01 08:32:54 PM PDT 24 |
15363405780 ps |
| T354 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1232978378 |
|
|
Jul 01 07:11:11 PM PDT 24 |
Jul 01 07:20:45 PM PDT 24 |
4777675122 ps |
| T342 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.4020393940 |
|
|
Jul 01 07:42:36 PM PDT 24 |
Jul 01 07:52:11 PM PDT 24 |
4925533474 ps |
| T162 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3285118414 |
|
|
Jul 01 07:47:13 PM PDT 24 |
Jul 01 07:54:54 PM PDT 24 |
3733789228 ps |
| T73 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3859225318 |
|
|
Jul 01 07:15:13 PM PDT 24 |
Jul 01 07:18:19 PM PDT 24 |
2894918001 ps |
| T106 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2588459158 |
|
|
Jul 01 07:12:46 PM PDT 24 |
Jul 01 07:16:32 PM PDT 24 |
2380983470 ps |
| T68 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.3000438975 |
|
|
Jul 01 07:33:47 PM PDT 24 |
Jul 01 10:48:59 PM PDT 24 |
64448971380 ps |
| T172 |
/workspace/coverage/default/4.chip_tap_straps_prod.2516567423 |
|
|
Jul 01 07:39:25 PM PDT 24 |
Jul 01 07:41:52 PM PDT 24 |
2825713361 ps |
| T109 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1873260236 |
|
|
Jul 01 07:13:57 PM PDT 24 |
Jul 01 07:39:31 PM PDT 24 |
11136762282 ps |
| T117 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3777683498 |
|
|
Jul 01 07:16:33 PM PDT 24 |
Jul 01 08:01:52 PM PDT 24 |
30598448548 ps |
| T173 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.583194149 |
|
|
Jul 01 07:26:52 PM PDT 24 |
Jul 01 07:32:07 PM PDT 24 |
5584060160 ps |
| T174 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2969644864 |
|
|
Jul 01 07:43:02 PM PDT 24 |
Jul 01 08:57:30 PM PDT 24 |
15416257246 ps |
| T175 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2446272358 |
|
|
Jul 01 07:20:45 PM PDT 24 |
Jul 01 07:26:07 PM PDT 24 |
4968951480 ps |
| T78 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2516699800 |
|
|
Jul 01 07:27:57 PM PDT 24 |
Jul 01 07:47:16 PM PDT 24 |
10550285725 ps |
| T147 |
/workspace/coverage/default/0.chip_sw_aes_enc.320303713 |
|
|
Jul 01 07:11:18 PM PDT 24 |
Jul 01 07:16:32 PM PDT 24 |
3252662320 ps |
| T525 |
/workspace/coverage/default/2.chip_sw_aes_entropy.710419515 |
|
|
Jul 01 07:31:45 PM PDT 24 |
Jul 01 07:35:38 PM PDT 24 |
2554070530 ps |
| T74 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1651814331 |
|
|
Jul 01 07:12:07 PM PDT 24 |
Jul 01 07:17:05 PM PDT 24 |
2791773354 ps |
| T526 |
/workspace/coverage/default/0.chip_sw_aes_entropy.139266801 |
|
|
Jul 01 07:12:21 PM PDT 24 |
Jul 01 07:16:03 PM PDT 24 |
2922151192 ps |
| T281 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1364581448 |
|
|
Jul 01 07:43:15 PM PDT 24 |
Jul 01 07:50:11 PM PDT 24 |
3512320760 ps |
| T271 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.1731053108 |
|
|
Jul 01 07:26:54 PM PDT 24 |
Jul 01 07:31:08 PM PDT 24 |
3303260660 ps |
| T328 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1641678611 |
|
|
Jul 01 07:34:37 PM PDT 24 |
Jul 01 07:45:34 PM PDT 24 |
5303004834 ps |
| T269 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3098042162 |
|
|
Jul 01 07:38:24 PM PDT 24 |
Jul 01 08:03:02 PM PDT 24 |
9389706888 ps |
| T183 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.540709387 |
|
|
Jul 01 07:11:07 PM PDT 24 |
Jul 01 07:28:39 PM PDT 24 |
5766575218 ps |
| T135 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1802628029 |
|
|
Jul 01 07:17:20 PM PDT 24 |
Jul 01 08:20:58 PM PDT 24 |
13271919448 ps |
| T140 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3804747957 |
|
|
Jul 01 07:28:58 PM PDT 24 |
Jul 01 08:09:15 PM PDT 24 |
13175693080 ps |
| T279 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3809009481 |
|
|
Jul 01 07:11:50 PM PDT 24 |
Jul 01 07:21:56 PM PDT 24 |
5938389644 ps |
| T63 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2879896338 |
|
|
Jul 01 07:14:23 PM PDT 24 |
Jul 01 08:06:26 PM PDT 24 |
24158691647 ps |
| T110 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2540764307 |
|
|
Jul 01 07:11:08 PM PDT 24 |
Jul 01 07:43:26 PM PDT 24 |
13926443438 ps |
| T296 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.684674019 |
|
|
Jul 01 07:41:42 PM PDT 24 |
Jul 01 07:51:01 PM PDT 24 |
3786527384 ps |
| T151 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.759414672 |
|
|
Jul 01 07:16:54 PM PDT 24 |
Jul 01 07:22:13 PM PDT 24 |
2968563248 ps |
| T55 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2936013501 |
|
|
Jul 01 07:18:27 PM PDT 24 |
Jul 01 08:37:51 PM PDT 24 |
17630613562 ps |
| T132 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.2857965575 |
|
|
Jul 01 07:23:52 PM PDT 24 |
Jul 01 07:57:46 PM PDT 24 |
7858692632 ps |
| T266 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.3374322948 |
|
|
Jul 01 07:08:52 PM PDT 24 |
Jul 01 07:19:06 PM PDT 24 |
4653200864 ps |
| T297 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.284149979 |
|
|
Jul 01 07:42:26 PM PDT 24 |
Jul 01 07:50:25 PM PDT 24 |
6034968568 ps |
| T202 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.425665774 |
|
|
Jul 01 07:41:01 PM PDT 24 |
Jul 01 07:51:20 PM PDT 24 |
5070546364 ps |
| T184 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.550600463 |
|
|
Jul 01 07:22:30 PM PDT 24 |
Jul 01 10:59:40 PM PDT 24 |
256037989808 ps |
| T527 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.707643579 |
|
|
Jul 01 07:10:22 PM PDT 24 |
Jul 01 07:21:51 PM PDT 24 |
7666117320 ps |
| T360 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3729212927 |
|
|
Jul 01 07:29:01 PM PDT 24 |
Jul 01 07:39:18 PM PDT 24 |
6974026200 ps |
| T88 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1574858830 |
|
|
Jul 01 07:33:10 PM PDT 24 |
Jul 01 07:47:32 PM PDT 24 |
7579639000 ps |
| T334 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1520311566 |
|
|
Jul 01 07:26:30 PM PDT 24 |
Jul 01 07:46:53 PM PDT 24 |
9711617018 ps |
| T359 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1579885268 |
|
|
Jul 01 07:39:09 PM PDT 24 |
Jul 01 07:45:46 PM PDT 24 |
3922487578 ps |
| T193 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3330477097 |
|
|
Jul 01 07:23:26 PM PDT 24 |
Jul 01 08:28:23 PM PDT 24 |
16910331026 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3490969364 |
|
|
Jul 01 07:09:40 PM PDT 24 |
Jul 01 07:16:58 PM PDT 24 |
5362656422 ps |
| T267 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2008629885 |
|
|
Jul 01 07:38:59 PM PDT 24 |
Jul 01 08:04:16 PM PDT 24 |
8903599270 ps |
| T237 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3145840775 |
|
|
Jul 01 07:12:48 PM PDT 24 |
Jul 01 07:19:59 PM PDT 24 |
5234301256 ps |
| T259 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1900211262 |
|
|
Jul 01 07:12:54 PM PDT 24 |
Jul 01 07:24:43 PM PDT 24 |
4888443932 ps |
| T339 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.928995237 |
|
|
Jul 01 07:26:49 PM PDT 24 |
Jul 01 08:26:28 PM PDT 24 |
14757666188 ps |
| T152 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2312220153 |
|
|
Jul 01 07:42:00 PM PDT 24 |
Jul 01 07:53:36 PM PDT 24 |
6084185736 ps |
| T528 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2319432428 |
|
|
Jul 01 07:29:57 PM PDT 24 |
Jul 01 07:38:49 PM PDT 24 |
4817029404 ps |
| T87 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1767197537 |
|
|
Jul 01 07:27:42 PM PDT 24 |
Jul 01 07:37:03 PM PDT 24 |
6890692764 ps |
| T529 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1053834265 |
|
|
Jul 01 07:29:56 PM PDT 24 |
Jul 01 07:43:53 PM PDT 24 |
8962164530 ps |
| T270 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.3463491527 |
|
|
Jul 01 07:28:21 PM PDT 24 |
Jul 01 07:32:22 PM PDT 24 |
3125211120 ps |
| T158 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3198405376 |
|
|
Jul 01 07:12:03 PM PDT 24 |
Jul 01 07:16:03 PM PDT 24 |
2995505321 ps |
| T130 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.1569029088 |
|
|
Jul 01 07:11:14 PM PDT 24 |
Jul 01 07:26:17 PM PDT 24 |
5065614496 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.262477145 |
|
|
Jul 01 07:27:19 PM PDT 24 |
Jul 01 07:42:44 PM PDT 24 |
4692368619 ps |
| T397 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.888254502 |
|
|
Jul 01 07:14:08 PM PDT 24 |
Jul 01 07:17:22 PM PDT 24 |
2161449816 ps |
| T204 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.1245962227 |
|
|
Jul 01 07:42:01 PM PDT 24 |
Jul 01 07:52:18 PM PDT 24 |
4502305768 ps |
| T530 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.95201313 |
|
|
Jul 01 07:22:34 PM PDT 24 |
Jul 01 07:33:48 PM PDT 24 |
8038364600 ps |
| T105 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2406179407 |
|
|
Jul 01 07:39:54 PM PDT 24 |
Jul 01 07:55:18 PM PDT 24 |
9980388895 ps |
| T133 |
/workspace/coverage/default/0.chip_sw_hmac_enc.3753055415 |
|
|
Jul 01 07:11:26 PM PDT 24 |
Jul 01 07:15:11 PM PDT 24 |
2712726936 ps |
| T77 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1521427059 |
|
|
Jul 01 07:32:56 PM PDT 24 |
Jul 01 07:43:56 PM PDT 24 |
4285328332 ps |
| T56 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1691729741 |
|
|
Jul 01 07:25:22 PM PDT 24 |
Jul 01 08:26:03 PM PDT 24 |
14478108457 ps |
| T403 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3676938082 |
|
|
Jul 01 07:46:36 PM PDT 24 |
Jul 01 07:51:37 PM PDT 24 |
3655116794 ps |
| T284 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3737021824 |
|
|
Jul 01 07:18:59 PM PDT 24 |
Jul 01 09:16:40 PM PDT 24 |
23916255400 ps |
| T485 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.4261978130 |
|
|
Jul 01 07:43:42 PM PDT 24 |
Jul 01 07:51:58 PM PDT 24 |
5675030560 ps |
| T531 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2085989785 |
|
|
Jul 01 07:23:48 PM PDT 24 |
Jul 01 07:41:56 PM PDT 24 |
5095548310 ps |
| T123 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.515880504 |
|
|
Jul 01 07:10:51 PM PDT 24 |
Jul 01 07:16:46 PM PDT 24 |
9624200603 ps |
| T153 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1223950074 |
|
|
Jul 01 07:25:27 PM PDT 24 |
Jul 01 07:36:03 PM PDT 24 |
9232112824 ps |
| T373 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.4220679647 |
|
|
Jul 01 07:43:03 PM PDT 24 |
Jul 01 07:52:34 PM PDT 24 |
4137639144 ps |
| T288 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.2439297049 |
|
|
Jul 01 07:34:33 PM PDT 24 |
Jul 01 07:38:51 PM PDT 24 |
2708493040 ps |
| T212 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1845784297 |
|
|
Jul 01 07:37:17 PM PDT 24 |
Jul 01 07:45:00 PM PDT 24 |
6428894926 ps |
| T532 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3910809372 |
|
|
Jul 01 07:13:18 PM PDT 24 |
Jul 01 07:29:17 PM PDT 24 |
5693065978 ps |
| T410 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.195642362 |
|
|
Jul 01 07:25:57 PM PDT 24 |
Jul 01 07:51:46 PM PDT 24 |
6494487600 ps |
| T272 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1271037233 |
|
|
Jul 01 07:11:21 PM PDT 24 |
Jul 01 07:16:46 PM PDT 24 |
3413090312 ps |
| T404 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.450266576 |
|
|
Jul 01 07:46:42 PM PDT 24 |
Jul 01 07:52:23 PM PDT 24 |
3746206936 ps |
| T197 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3707001296 |
|
|
Jul 01 07:43:02 PM PDT 24 |
Jul 01 07:48:47 PM PDT 24 |
4056454024 ps |
| T413 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.68643721 |
|
|
Jul 01 07:41:09 PM PDT 24 |
Jul 01 07:47:53 PM PDT 24 |
3978054544 ps |
| T32 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.2787087202 |
|
|
Jul 01 07:09:29 PM PDT 24 |
Jul 01 07:14:31 PM PDT 24 |
3131561832 ps |
| T392 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.510740602 |
|
|
Jul 01 07:30:11 PM PDT 24 |
Jul 01 08:41:05 PM PDT 24 |
15293136858 ps |
| T280 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.561452894 |
|
|
Jul 01 07:29:12 PM PDT 24 |
Jul 01 07:38:20 PM PDT 24 |
6043684830 ps |
| T533 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.3171226468 |
|
|
Jul 01 07:17:35 PM PDT 24 |
Jul 01 07:20:37 PM PDT 24 |
2971441450 ps |
| T534 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1956987235 |
|
|
Jul 01 07:21:04 PM PDT 24 |
Jul 01 07:35:38 PM PDT 24 |
8216568508 ps |
| T124 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.4085576151 |
|
|
Jul 01 07:31:49 PM PDT 24 |
Jul 01 07:38:13 PM PDT 24 |
2964399720 ps |
| T262 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2535480863 |
|
|
Jul 01 07:15:47 PM PDT 24 |
Jul 01 07:36:43 PM PDT 24 |
4950356856 ps |
| T535 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.245201678 |
|
|
Jul 01 07:38:34 PM PDT 24 |
Jul 01 08:36:01 PM PDT 24 |
14500664368 ps |
| T282 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2373838643 |
|
|
Jul 01 07:43:02 PM PDT 24 |
Jul 01 07:48:28 PM PDT 24 |
3767070134 ps |
| T80 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.323993372 |
|
|
Jul 01 07:30:37 PM PDT 24 |
Jul 01 07:40:47 PM PDT 24 |
3098398404 ps |
| T64 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.385496853 |
|
|
Jul 01 07:27:38 PM PDT 24 |
Jul 01 10:25:10 PM PDT 24 |
58464859544 ps |
| T155 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3813167148 |
|
|
Jul 01 07:36:49 PM PDT 24 |
Jul 01 07:47:21 PM PDT 24 |
5159637922 ps |
| T230 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1104194841 |
|
|
Jul 01 07:11:39 PM PDT 24 |
Jul 01 07:21:32 PM PDT 24 |
6951579760 ps |
| T395 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.937611280 |
|
|
Jul 01 07:41:08 PM PDT 24 |
Jul 01 07:52:39 PM PDT 24 |
5385192720 ps |
| T69 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2669131432 |
|
|
Jul 01 07:09:57 PM PDT 24 |
Jul 01 07:19:36 PM PDT 24 |
6298352900 ps |
| T380 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.3899578266 |
|
|
Jul 01 07:39:26 PM PDT 24 |
Jul 01 08:29:05 PM PDT 24 |
27140844478 ps |
| T125 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2216967694 |
|
|
Jul 01 07:37:58 PM PDT 24 |
Jul 01 07:49:40 PM PDT 24 |
5780299602 ps |
| T536 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4250384830 |
|
|
Jul 01 07:40:09 PM PDT 24 |
Jul 01 07:49:18 PM PDT 24 |
3875915674 ps |
| T191 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3843346208 |
|
|
Jul 01 07:28:04 PM PDT 24 |
Jul 01 07:43:45 PM PDT 24 |
5468365466 ps |
| T283 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.4168683454 |
|
|
Jul 01 07:42:37 PM PDT 24 |
Jul 01 07:50:20 PM PDT 24 |
3859525560 ps |
| T33 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3372746683 |
|
|
Jul 01 07:33:33 PM PDT 24 |
Jul 01 07:39:11 PM PDT 24 |
5274039976 ps |
| T537 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2004508063 |
|
|
Jul 01 07:34:34 PM PDT 24 |
Jul 01 07:37:26 PM PDT 24 |
2097549414 ps |
| T298 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.383650094 |
|
|
Jul 01 07:16:27 PM PDT 24 |
Jul 01 08:18:29 PM PDT 24 |
24259550588 ps |
| T341 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.4094358320 |
|
|
Jul 01 07:44:09 PM PDT 24 |
Jul 01 07:55:16 PM PDT 24 |
5934763528 ps |
| T29 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1901192299 |
|
|
Jul 01 07:27:35 PM PDT 24 |
Jul 01 07:41:45 PM PDT 24 |
4540916420 ps |
| T79 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3928514402 |
|
|
Jul 01 07:11:22 PM PDT 24 |
Jul 01 07:21:11 PM PDT 24 |
18477528808 ps |
| T289 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1185419902 |
|
|
Jul 01 07:15:56 PM PDT 24 |
Jul 01 07:20:09 PM PDT 24 |
2654578592 ps |
| T261 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3976836932 |
|
|
Jul 01 07:24:56 PM PDT 24 |
Jul 01 07:35:30 PM PDT 24 |
4710867667 ps |
| T2 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3311263158 |
|
|
Jul 01 07:25:47 PM PDT 24 |
Jul 01 07:47:52 PM PDT 24 |
19382249690 ps |
| T199 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1315280773 |
|
|
Jul 01 07:29:01 PM PDT 24 |
Jul 01 07:33:44 PM PDT 24 |
2714354798 ps |
| T231 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2377433646 |
|
|
Jul 01 07:37:13 PM PDT 24 |
Jul 01 07:46:50 PM PDT 24 |
5990354221 ps |
| T538 |
/workspace/coverage/default/0.chip_sw_example_rom.2629593659 |
|
|
Jul 01 07:09:43 PM PDT 24 |
Jul 01 07:11:54 PM PDT 24 |
2691096880 ps |
| T75 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3106371478 |
|
|
Jul 01 07:32:17 PM PDT 24 |
Jul 01 07:48:04 PM PDT 24 |
5415464902 ps |
| T232 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1574899204 |
|
|
Jul 01 07:38:46 PM PDT 24 |
Jul 01 07:47:39 PM PDT 24 |
7209681492 ps |
| T3 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2337670902 |
|
|
Jul 01 07:17:59 PM PDT 24 |
Jul 01 07:25:43 PM PDT 24 |
5960626460 ps |
| T338 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1869288051 |
|
|
Jul 01 07:32:19 PM PDT 24 |
Jul 01 08:04:42 PM PDT 24 |
11585444184 ps |
| T144 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.480588816 |
|
|
Jul 01 07:34:50 PM PDT 24 |
Jul 01 07:44:41 PM PDT 24 |
4477234636 ps |
| T141 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2773077983 |
|
|
Jul 01 07:25:16 PM PDT 24 |
Jul 01 07:30:18 PM PDT 24 |
3100129446 ps |
| T384 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1799959420 |
|
|
Jul 01 07:44:25 PM PDT 24 |
Jul 01 07:49:38 PM PDT 24 |
3954419640 ps |
| T390 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.1404320995 |
|
|
Jul 01 07:28:50 PM PDT 24 |
Jul 01 07:38:30 PM PDT 24 |
4562993078 ps |
| T52 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.1971830593 |
|
|
Jul 01 07:28:52 PM PDT 24 |
Jul 01 07:34:00 PM PDT 24 |
2713812447 ps |
| T358 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.854321389 |
|
|
Jul 01 07:41:14 PM PDT 24 |
Jul 01 07:48:12 PM PDT 24 |
3799888786 ps |
| T209 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1552814656 |
|
|
Jul 01 07:14:55 PM PDT 24 |
Jul 01 08:46:37 PM PDT 24 |
43143225854 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.624876266 |
|
|
Jul 01 07:10:00 PM PDT 24 |
Jul 01 07:43:54 PM PDT 24 |
25129978078 ps |
| T391 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1281816460 |
|
|
Jul 01 07:37:23 PM PDT 24 |
Jul 01 07:55:42 PM PDT 24 |
8135691488 ps |
| T116 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.2360059344 |
|
|
Jul 01 07:13:58 PM PDT 24 |
Jul 01 07:26:06 PM PDT 24 |
6077067682 ps |
| T351 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2324162273 |
|
|
Jul 01 07:37:23 PM PDT 24 |
Jul 01 07:41:44 PM PDT 24 |
2930934040 ps |
| T81 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.2874517902 |
|
|
Jul 01 07:10:13 PM PDT 24 |
Jul 01 07:31:46 PM PDT 24 |
6147012808 ps |
| T36 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.936971771 |
|
|
Jul 01 07:10:52 PM PDT 24 |
Jul 01 07:15:59 PM PDT 24 |
3616036482 ps |
| T219 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3185277526 |
|
|
Jul 01 07:11:00 PM PDT 24 |
Jul 01 07:25:06 PM PDT 24 |
4916366504 ps |
| T104 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3558218484 |
|
|
Jul 01 07:27:35 PM PDT 24 |
Jul 01 07:37:08 PM PDT 24 |
4586122062 ps |
| T101 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1268657016 |
|
|
Jul 01 07:39:32 PM PDT 24 |
Jul 01 07:48:53 PM PDT 24 |
4520740596 ps |
| T539 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1253356293 |
|
|
Jul 01 07:10:35 PM PDT 24 |
Jul 01 07:32:46 PM PDT 24 |
5978107480 ps |
| T540 |
/workspace/coverage/default/2.chip_sw_example_flash.3449338252 |
|
|
Jul 01 07:25:35 PM PDT 24 |
Jul 01 07:29:19 PM PDT 24 |
2972528226 ps |
| T502 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1001797792 |
|
|
Jul 01 07:42:16 PM PDT 24 |
Jul 01 07:48:19 PM PDT 24 |
4037379556 ps |
| T126 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.283965702 |
|
|
Jul 01 07:25:15 PM PDT 24 |
Jul 01 07:30:02 PM PDT 24 |
2365763164 ps |
| T8 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1471579997 |
|
|
Jul 01 07:16:41 PM PDT 24 |
Jul 01 07:44:54 PM PDT 24 |
14581746234 ps |
| T419 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3282742951 |
|
|
Jul 01 07:38:18 PM PDT 24 |
Jul 01 07:43:56 PM PDT 24 |
4041871548 ps |
| T76 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2873348622 |
|
|
Jul 01 07:28:07 PM PDT 24 |
Jul 01 07:37:09 PM PDT 24 |
4808274817 ps |
| T420 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2305339326 |
|
|
Jul 01 07:09:59 PM PDT 24 |
Jul 01 07:13:33 PM PDT 24 |
2847739700 ps |
| T355 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2828170871 |
|
|
Jul 01 07:41:56 PM PDT 24 |
Jul 01 07:52:57 PM PDT 24 |
5980168752 ps |
| T203 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1173733349 |
|
|
Jul 01 07:27:42 PM PDT 24 |
Jul 01 07:29:42 PM PDT 24 |
2164257964 ps |
| T51 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1292927917 |
|
|
Jul 01 07:20:25 PM PDT 24 |
Jul 01 07:29:02 PM PDT 24 |
5386470390 ps |
| T421 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.3626777578 |
|
|
Jul 01 07:26:39 PM PDT 24 |
Jul 01 07:38:02 PM PDT 24 |
4740558184 ps |
| T422 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.827783162 |
|
|
Jul 01 07:16:00 PM PDT 24 |
Jul 01 07:34:32 PM PDT 24 |
5382201624 ps |
| T423 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1645961875 |
|
|
Jul 01 07:28:56 PM PDT 24 |
Jul 01 07:37:29 PM PDT 24 |
7229549624 ps |
| T37 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.2760474245 |
|
|
Jul 01 07:11:16 PM PDT 24 |
Jul 01 08:10:59 PM PDT 24 |
11900311428 ps |
| T424 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2661650509 |
|
|
Jul 01 07:30:36 PM PDT 24 |
Jul 01 07:41:12 PM PDT 24 |
4063584722 ps |
| T196 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.533819918 |
|
|
Jul 01 07:43:33 PM PDT 24 |
Jul 01 07:49:41 PM PDT 24 |
3119896968 ps |
| T7 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2925540439 |
|
|
Jul 01 07:25:38 PM PDT 24 |
Jul 01 07:48:42 PM PDT 24 |
20130882640 ps |
| T372 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.47388903 |
|
|
Jul 01 07:40:52 PM PDT 24 |
Jul 01 07:51:08 PM PDT 24 |
5790251368 ps |
| T182 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.3624694110 |
|
|
Jul 01 07:12:59 PM PDT 24 |
Jul 01 07:23:06 PM PDT 24 |
3016903284 ps |
| T399 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.247319262 |
|
|
Jul 01 07:45:32 PM PDT 24 |
Jul 01 07:50:55 PM PDT 24 |
3232184188 ps |
| T102 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.3462953611 |
|
|
Jul 01 07:25:41 PM PDT 24 |
Jul 01 07:31:22 PM PDT 24 |
4723432816 ps |
| T541 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.3805494270 |
|
|
Jul 01 07:39:59 PM PDT 24 |
Jul 01 08:34:18 PM PDT 24 |
16161990016 ps |
| T443 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.676798868 |
|
|
Jul 01 07:45:57 PM PDT 24 |
Jul 01 07:51:56 PM PDT 24 |
4108902320 ps |
| T299 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2199208357 |
|
|
Jul 01 07:29:20 PM PDT 24 |
Jul 01 08:23:08 PM PDT 24 |
14467281775 ps |
| T263 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.288974812 |
|
|
Jul 01 07:44:48 PM PDT 24 |
Jul 01 07:55:41 PM PDT 24 |
5146190604 ps |
| T255 |
/workspace/coverage/default/1.chip_sw_flash_init.3634119649 |
|
|
Jul 01 07:15:40 PM PDT 24 |
Jul 01 07:47:40 PM PDT 24 |
16064560086 ps |
| T210 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2774203117 |
|
|
Jul 01 07:18:36 PM PDT 24 |
Jul 01 08:42:07 PM PDT 24 |
49722794600 ps |
| T264 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.741638704 |
|
|
Jul 01 07:44:46 PM PDT 24 |
Jul 01 07:52:27 PM PDT 24 |
3564413432 ps |
| T30 |
/workspace/coverage/default/1.chip_sw_gpio.114533167 |
|
|
Jul 01 07:17:31 PM PDT 24 |
Jul 01 07:25:16 PM PDT 24 |
3738092340 ps |
| T163 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.3364926097 |
|
|
Jul 01 07:31:32 PM PDT 24 |
Jul 01 07:36:46 PM PDT 24 |
3449754062 ps |
| T346 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.1451055329 |
|
|
Jul 01 07:09:17 PM PDT 24 |
Jul 01 07:13:52 PM PDT 24 |
2982966512 ps |
| T86 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3025232463 |
|
|
Jul 01 07:11:51 PM PDT 24 |
Jul 01 07:35:53 PM PDT 24 |
7847736020 ps |
| T347 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1455792504 |
|
|
Jul 01 07:16:37 PM PDT 24 |
Jul 01 07:34:31 PM PDT 24 |
6672093496 ps |
| T257 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.329380400 |
|
|
Jul 01 07:18:42 PM PDT 24 |
Jul 01 07:26:29 PM PDT 24 |
4194382558 ps |
| T542 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1551892339 |
|
|
Jul 01 07:09:35 PM PDT 24 |
Jul 01 07:21:14 PM PDT 24 |
4658202640 ps |
| T543 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2403208722 |
|
|
Jul 01 07:23:56 PM PDT 24 |
Jul 01 07:45:48 PM PDT 24 |
6927315666 ps |
| T300 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.218727536 |
|
|
Jul 01 07:09:14 PM PDT 24 |
Jul 01 07:10:59 PM PDT 24 |
2465057290 ps |
| T121 |
/workspace/coverage/default/0.chip_sw_alert_test.1726761358 |
|
|
Jul 01 07:13:22 PM PDT 24 |
Jul 01 07:19:09 PM PDT 24 |
3058782682 ps |
| T544 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.772476252 |
|
|
Jul 01 07:16:41 PM PDT 24 |
Jul 01 07:35:28 PM PDT 24 |
6421551477 ps |
| T545 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2422605338 |
|
|
Jul 01 07:25:07 PM PDT 24 |
Jul 01 08:02:44 PM PDT 24 |
25597557608 ps |
| T546 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.3957372772 |
|
|
Jul 01 07:31:45 PM PDT 24 |
Jul 01 07:36:53 PM PDT 24 |
3215025632 ps |
| T250 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1878696760 |
|
|
Jul 01 07:28:16 PM PDT 24 |
Jul 01 08:55:03 PM PDT 24 |
48262267200 ps |
| T547 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1040751381 |
|
|
Jul 01 07:25:47 PM PDT 24 |
Jul 01 07:32:08 PM PDT 24 |
2873492900 ps |
| T111 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2419779513 |
|
|
Jul 01 07:15:12 PM PDT 24 |
Jul 01 07:24:16 PM PDT 24 |
3616923740 ps |
| T333 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1214742467 |
|
|
Jul 01 07:17:32 PM PDT 24 |
Jul 01 07:51:41 PM PDT 24 |
9032960472 ps |
| T217 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3749758636 |
|
|
Jul 01 07:37:36 PM PDT 24 |
Jul 01 07:42:39 PM PDT 24 |
3473448946 ps |
| T440 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.227384077 |
|
|
Jul 01 07:43:50 PM PDT 24 |
Jul 01 07:50:44 PM PDT 24 |
3882941264 ps |
| T548 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.4196079172 |
|
|
Jul 01 07:40:01 PM PDT 24 |
Jul 01 07:44:28 PM PDT 24 |
2862957948 ps |
| T45 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1448045275 |
|
|
Jul 01 07:15:02 PM PDT 24 |
Jul 01 07:19:14 PM PDT 24 |
3270791750 ps |
| T549 |
/workspace/coverage/default/0.rom_e2e_smoke.2534317770 |
|
|
Jul 01 07:24:55 PM PDT 24 |
Jul 01 08:36:40 PM PDT 24 |
14515598836 ps |
| T435 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.231970867 |
|
|
Jul 01 07:41:55 PM PDT 24 |
Jul 01 07:49:34 PM PDT 24 |
5625688130 ps |
| T166 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.434574859 |
|
|
Jul 01 07:43:51 PM PDT 24 |
Jul 01 07:50:12 PM PDT 24 |
4360471064 ps |
| T53 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.1773565484 |
|
|
Jul 01 07:20:24 PM PDT 24 |
Jul 01 07:25:40 PM PDT 24 |
3282989272 ps |
| T315 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1637500138 |
|
|
Jul 01 07:35:54 PM PDT 24 |
Jul 01 07:49:15 PM PDT 24 |
6485526792 ps |
| T550 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.88054646 |
|
|
Jul 01 07:22:52 PM PDT 24 |
Jul 01 07:28:16 PM PDT 24 |
3400353804 ps |
| T411 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.1051594233 |
|
|
Jul 01 07:26:00 PM PDT 24 |
Jul 01 07:31:51 PM PDT 24 |
3291782453 ps |
| T278 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3229507845 |
|
|
Jul 01 07:43:00 PM PDT 24 |
Jul 01 07:49:01 PM PDT 24 |
3343798408 ps |
| T551 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.4237756898 |
|
|
Jul 01 07:36:05 PM PDT 24 |
Jul 01 08:38:39 PM PDT 24 |
24403726355 ps |
| T552 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.738510055 |
|
|
Jul 01 07:14:19 PM PDT 24 |
Jul 01 07:19:07 PM PDT 24 |
3003966350 ps |
| T521 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2824696120 |
|
|
Jul 01 07:44:56 PM PDT 24 |
Jul 01 07:56:58 PM PDT 24 |
5960274040 ps |
| T381 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4010101024 |
|
|
Jul 01 07:13:01 PM PDT 24 |
Jul 01 07:18:44 PM PDT 24 |
6443622324 ps |
| T145 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1401371611 |
|
|
Jul 01 07:44:47 PM PDT 24 |
Jul 01 07:56:07 PM PDT 24 |
5778743828 ps |