Line Coverage for Module :
pinmux
| Line No. | Total | Covered | Percent |
TOTAL | | 1279 | 1017 | 79.52 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
ALWAYS | 162 | 45 | 45 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 0 | 0.00 |
CONT_ASSIGN | 250 | 1 | 0 | 0.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 251 | 1 | 0 | 0.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 253 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 254 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 255 | 1 | 0 | 0.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 0 | 0.00 |
CONT_ASSIGN | 258 | 1 | 0 | 0.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 274 | 1 | 0 | 0.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 276 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 277 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 278 | 1 | 0 | 0.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 320 | 0 | 0 | |
CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
ALWAYS | 423 | 15 | 15 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 511 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
ALWAYS | 552 | 3 | 2 | 66.67 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 581 | 1 | 1 | 100.00 |
CONT_ASSIGN | 586 | 1 | 1 | 100.00 |
CONT_ASSIGN | 591 | 1 | 1 | 100.00 |
CONT_ASSIGN | 591 | 1 | 1 | 100.00 |
CONT_ASSIGN | 591 | 1 | 1 | 100.00 |
CONT_ASSIGN | 591 | 1 | 1 | 100.00 |
CONT_ASSIGN | 591 | 1 | 1 | 100.00 |
CONT_ASSIGN | 591 | 1 | 1 | 100.00 |
CONT_ASSIGN | 591 | 1 | 1 | 100.00 |
CONT_ASSIGN | 591 | 1 | 1 | 100.00 |
CONT_ASSIGN | 612 | 1 | 1 | 100.00 |
CONT_ASSIGN | 612 | 1 | 0 | 0.00 |
CONT_ASSIGN | 612 | 1 | 1 | 100.00 |
CONT_ASSIGN | 612 | 1 | 0 | 0.00 |
CONT_ASSIGN | 612 | 1 | 0 | 0.00 |
CONT_ASSIGN | 612 | 1 | 1 | 100.00 |
CONT_ASSIGN | 612 | 1 | 0 | 0.00 |
CONT_ASSIGN | 612 | 1 | 0 | 0.00 |
CONT_ASSIGN | 616 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
133 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
|
|
|
MISSING_ELSE |
171 |
1 |
1 |
172 |
1 |
1 |
|
|
|
MISSING_ELSE |
174 |
1 |
1 |
175 |
1 |
1 |
|
|
|
MISSING_ELSE |
177 |
1 |
1 |
178 |
1 |
1 |
|
|
|
MISSING_ELSE |
180 |
1 |
1 |
181 |
1 |
1 |
|
|
|
MISSING_ELSE |
183 |
1 |
1 |
184 |
1 |
1 |
|
|
|
MISSING_ELSE |
186 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
189 |
1 |
1 |
190 |
1 |
1 |
|
|
|
MISSING_ELSE |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
195 |
1 |
1 |
196 |
1 |
1 |
|
|
|
MISSING_ELSE |
200 |
1 |
1 |
201 |
1 |
1 |
202 |
1 |
1 |
|
|
|
MISSING_ELSE |
204 |
1 |
1 |
205 |
1 |
1 |
|
|
|
MISSING_ELSE |
207 |
1 |
1 |
208 |
1 |
1 |
|
|
|
MISSING_ELSE |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
213 |
1 |
1 |
214 |
1 |
1 |
|
|
|
MISSING_ELSE |
216 |
1 |
1 |
217 |
1 |
1 |
|
|
|
MISSING_ELSE |
219 |
1 |
1 |
220 |
1 |
1 |
|
|
|
MISSING_ELSE |
222 |
1 |
1 |
223 |
1 |
1 |
|
|
|
MISSING_ELSE |
225 |
1 |
1 |
226 |
1 |
1 |
|
|
|
MISSING_ELSE |
228 |
1 |
1 |
229 |
1 |
1 |
|
|
|
MISSING_ELSE |
249 |
16 |
16 |
250 |
14 |
16 |
251 |
0 |
16 |
252 |
16 |
16 |
253 |
0 |
16 |
254 |
0 |
16 |
255 |
0 |
16 |
256 |
16 |
16 |
257 |
16 |
16 |
258 |
14 |
16 |
259 |
16 |
16 |
272 |
47 |
47 |
273 |
47 |
47 |
274 |
0 |
47 |
275 |
47 |
47 |
276 |
0 |
47 |
277 |
0 |
47 |
278 |
0 |
47 |
279 |
47 |
47 |
280 |
47 |
47 |
281 |
47 |
47 |
282 |
47 |
47 |
320 |
|
unreachable |
321 |
1 |
1 |
420 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
425 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
428 |
1 |
1 |
430 |
1 |
1 |
433 |
1 |
1 |
434 |
1 |
1 |
435 |
1 |
1 |
436 |
1 |
1 |
|
|
|
MISSING_ELSE |
441 |
1 |
1 |
442 |
1 |
1 |
443 |
1 |
1 |
444 |
1 |
1 |
|
|
|
MISSING_ELSE |
460 |
1 |
1 |
464 |
57 |
57 |
474 |
1 |
1 |
475 |
1 |
1 |
479 |
47 |
47 |
483 |
47 |
47 |
492 |
47 |
47 |
496 |
47 |
47 |
501 |
47 |
47 |
503 |
47 |
47 |
511 |
1 |
1 |
515 |
16 |
16 |
519 |
16 |
16 |
528 |
16 |
16 |
532 |
16 |
16 |
537 |
16 |
16 |
539 |
16 |
16 |
552 |
1 |
1 |
553 |
1 |
1 |
554 |
0 |
1 |
|
|
|
MISSING_ELSE |
558 |
15 |
15 |
572 |
47 |
47 |
581 |
1 |
1 |
586 |
1 |
1 |
591 |
8 |
8 |
612 |
3 |
8 |
616 |
1 |
1 |
Cond Coverage for Module :
pinmux
| Total | Covered | Percent |
Conditions | 1975 | 1747 | 88.46 |
Logical | 1975 | 1747 | 88.46 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Toggle Coverage for Module :
pinmux
| Total | Covered | Percent |
Totals |
713 |
389 |
54.56 |
Total Bits |
3068 |
2028 |
66.10 |
Total Bits 0->1 |
1534 |
1015 |
66.17 |
Total Bits 1->0 |
1534 |
1013 |
66.04 |
| | | |
Ports |
713 |
389 |
54.56 |
Port Bits |
3068 |
2028 |
66.10 |
Port Bits 0->1 |
1534 |
1015 |
66.17 |
Port Bits 1->0 |
1534 |
1013 |
66.04 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T5,T17,T19 |
Yes |
T4,T5,T6 |
INPUT |
rst_sys_ni |
Yes |
Yes |
T5,T17,T19 |
Yes |
T4,T5,T6 |
INPUT |
scanmode_i[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
clk_aon_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_aon_ni |
Yes |
Yes |
T5,T17,T19 |
Yes |
T4,T5,T6 |
INPUT |
pin_wkup_req_o |
Yes |
Yes |
T1,T2,T7 |
Yes |
T1,T2,T3 |
OUTPUT |
usb_wkup_req_o |
Yes |
Yes |
T1,T2,T7 |
Yes |
T1,T33,T2 |
OUTPUT |
sleep_en_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T5,T19,T20 |
INPUT |
strap_en_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
strap_en_override_i |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
lc_dft_en_i[3:0] |
Yes |
Yes |
T5,T17,T19 |
Yes |
T4,T5,T6 |
INPUT |
lc_hw_debug_en_i[3:0] |
Yes |
Yes |
T5,T17,T19 |
Yes |
T4,T5,T6 |
INPUT |
lc_check_byp_en_i[3:0] |
Yes |
Yes |
T60,T78,T158 |
Yes |
T60,T78,T158 |
INPUT |
lc_escalate_en_i[3:0] |
Yes |
Yes |
T5,T17,T114 |
Yes |
T5,T17,T114 |
INPUT |
pinmux_hw_debug_en_o[3:0] |
Yes |
Yes |
T5,T17,T19 |
Yes |
T4,T5,T6 |
OUTPUT |
dft_strap_test_o.straps[1:0] |
No |
No |
|
Yes |
T97,T98,T99 |
OUTPUT |
dft_strap_test_o.valid |
Yes |
Yes |
T5,T17,T19 |
Yes |
T4,T5,T6 |
OUTPUT |
dft_hold_tap_sel_i |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
lc_jtag_o.tdi |
Yes |
Yes |
T62,T59,T60 |
Yes |
T62,T59,T60 |
OUTPUT |
lc_jtag_o.trst_n |
Yes |
Yes |
T59,T60,T78 |
Yes |
T62,T59,T60 |
OUTPUT |
lc_jtag_o.tms |
Yes |
Yes |
T62,T59,T60 |
Yes |
T62,T59,T60 |
OUTPUT |
lc_jtag_o.tck |
Yes |
Yes |
T62,T59,T60 |
Yes |
T62,T59,T60 |
OUTPUT |
lc_jtag_i.tdo_oe |
Yes |
Yes |
T62,T59,T60 |
Yes |
T62,T59,T60 |
INPUT |
lc_jtag_i.tdo |
Yes |
Yes |
T62,T59,T60 |
Yes |
T62,T59,T60 |
INPUT |
rv_jtag_o.tdi |
Yes |
Yes |
T61,T117,T63 |
Yes |
T61,T117,T63 |
OUTPUT |
rv_jtag_o.trst_n |
Yes |
Yes |
T61,T64,T116 |
Yes |
T61,T117,T63 |
OUTPUT |
rv_jtag_o.tms |
Yes |
Yes |
T61,T117,T63 |
Yes |
T61,T117,T63 |
OUTPUT |
rv_jtag_o.tck |
Yes |
Yes |
T61,T117,T63 |
Yes |
T61,T117,T63 |
OUTPUT |
rv_jtag_i.tdo_oe |
Yes |
Yes |
T61,T117,T63 |
Yes |
T61,T117,T63 |
INPUT |
rv_jtag_i.tdo |
Yes |
Yes |
T61,T117,T63 |
Yes |
T61,T117,T63 |
INPUT |
dft_jtag_o.tdi |
Yes |
Yes |
T116,T97,T159 |
Yes |
T116,T97,T159 |
OUTPUT |
dft_jtag_o.trst_n |
Yes |
Yes |
T116,T97,T159 |
Yes |
T116,T97,T159 |
OUTPUT |
dft_jtag_o.tms |
Yes |
Yes |
T116,T159,T99 |
Yes |
T116,T159,T99 |
OUTPUT |
dft_jtag_o.tck |
Yes |
Yes |
T116,T97,T159 |
Yes |
T116,T97,T159 |
OUTPUT |
dft_jtag_i.tdo_oe |
Yes |
Yes |
T116,T97,T160 |
Yes |
T116,T97,T160 |
INPUT |
dft_jtag_i.tdo |
Yes |
Yes |
T116,T97,T160 |
Yes |
T116,T97,T160 |
INPUT |
usbdev_dppullup_en_i |
Yes |
Yes |
T31,T32,T33 |
Yes |
T31,T1,T32 |
INPUT |
usbdev_dnpullup_en_i |
Yes |
Yes |
T31,T32,T161 |
Yes |
T31,T32,T161 |
INPUT |
usb_dppullup_en_o |
Yes |
Yes |
T31,T1,T32 |
Yes |
T31,T1,T32 |
OUTPUT |
usb_dnpullup_en_o |
Yes |
Yes |
T31,T32,T161 |
Yes |
T31,T32,T161 |
OUTPUT |
usbdev_suspend_req_i |
Yes |
Yes |
T1,T33,T2 |
Yes |
T1,T33,T2 |
INPUT |
usbdev_wake_ack_i |
Yes |
Yes |
T1,T33,T2 |
Yes |
T1,T33,T2 |
INPUT |
usbdev_bus_not_idle_o |
Yes |
Yes |
T1,T2,T7 |
Yes |
T1,T2,T7 |
OUTPUT |
usbdev_bus_reset_o |
Yes |
Yes |
T161 |
Yes |
T161 |
OUTPUT |
usbdev_sense_lost_o |
Yes |
Yes |
T1,T2,T7 |
Yes |
T1,T33,T2 |
OUTPUT |
usbdev_wake_detect_active_o |
Yes |
Yes |
T1,T2,T7 |
Yes |
T1,T33,T2 |
OUTPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[0] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[2:1] |
No |
No |
|
No |
|
INPUT |
tl_i.a_user.instr_type[3] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[1:0] |
No |
No |
|
No |
|
INPUT |
tl_i.a_address[11:2] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[16:12] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[18:17] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[21:19] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[22] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:23] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T63,*T64,*T8 |
Yes |
T63,T64,T8 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[0] |
Yes |
Yes |
*T8,*T65,*T66 |
Yes |
T8,T65,T66 |
INPUT |
tl_i.a_opcode[1] |
No |
No |
|
No |
|
INPUT |
tl_i.a_opcode[2] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
tl_o.d_error |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
tl_o.d_user.rsp_intg[1:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
tl_o.d_user.rsp_intg[2] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_user.rsp_intg[5:3] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
tl_o.d_sink |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T8,*T139,*T11 |
Yes |
T8,T139,T11 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T162,T110,T163 |
Yes |
T162,T110,T163 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T110,T163,T164 |
Yes |
T110,T163,T164 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T110,T163,T164 |
Yes |
T110,T163,T164 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T162,T110,T163 |
Yes |
T162,T110,T163 |
OUTPUT |
periph_to_mio_i[74:0] |
Yes |
Yes |
T30,T39,T40 |
Yes |
T30,T39,T40 |
INPUT |
periph_to_mio_oe_i[74:0] |
Yes |
Yes |
T30,T40,T41 |
Yes |
T30,T39,T40 |
INPUT |
mio_to_periph_o[56:0] |
Yes |
Yes |
T30,T39,T40 |
Yes |
T30,T39,T40 |
OUTPUT |
periph_to_dio_i[11:0] |
Yes |
Yes |
*T31,*T1,*T32 |
Yes |
T31,T33,T2 |
INPUT |
periph_to_dio_i[13:12] |
No |
No |
|
No |
|
INPUT |
periph_to_dio_i[15:14] |
Yes |
Yes |
T25,T26,T27 |
Yes |
T25,T26,T27 |
INPUT |
periph_to_dio_oe_i[15:0] |
Yes |
Yes |
T31,T37,T38 |
Yes |
T31,T37,T38 |
INPUT |
dio_to_periph_o[15:0] |
Yes |
Yes |
T31,T32,T37 |
Yes |
T31,T32,T37 |
OUTPUT |
mio_attr_o[0].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[0].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[0].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[0].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[0].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[0].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[0].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[0].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[0].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[0].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[0].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[1].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[1].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[1].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[1].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[1].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[1].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[1].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[1].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[1].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[1].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[1].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[2].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[2].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[2].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
mio_attr_o[2].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
mio_attr_o[2].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[2].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[2].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[2].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[2].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[2].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[2].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[3].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[3].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[3].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[3].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[3].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[3].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[3].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[3].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[3].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[3].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[3].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[4].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[4].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[4].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[4].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[4].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[4].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[4].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[4].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[4].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[4].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[4].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[5].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[5].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[5].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[5].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[5].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[5].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[5].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[5].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[5].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[5].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[5].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[6].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[6].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[6].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[6].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[6].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[6].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[6].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[6].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[6].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[6].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[6].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[7].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[7].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[7].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T52,T53,T54 |
OUTPUT |
mio_attr_o[7].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T52,T53,T54 |
OUTPUT |
mio_attr_o[7].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[7].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[7].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[7].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[7].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[7].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[7].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[8].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[8].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[8].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[8].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[8].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[8].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[8].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[8].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[8].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[8].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[8].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[9].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[9].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[9].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
mio_attr_o[9].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
mio_attr_o[9].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[9].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[9].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[9].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[9].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[9].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[9].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[10].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[10].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[10].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T25 |
OUTPUT |
mio_attr_o[10].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T25 |
OUTPUT |
mio_attr_o[10].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[10].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[10].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[10].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[10].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[10].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[10].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[11].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[11].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[11].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[11].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[11].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[11].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[11].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[11].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[11].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[11].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[11].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[12].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[12].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[12].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T25 |
OUTPUT |
mio_attr_o[12].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T25 |
OUTPUT |
mio_attr_o[12].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[12].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[12].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[12].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[12].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[12].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[12].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[13].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[13].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[13].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
mio_attr_o[13].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
mio_attr_o[13].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[13].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[13].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[13].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[13].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[13].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[13].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[14].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[14].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[14].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
mio_attr_o[14].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
mio_attr_o[14].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[14].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[14].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[14].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[14].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[14].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[14].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[15].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[15].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[15].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
mio_attr_o[15].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
mio_attr_o[15].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[15].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[15].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[15].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[15].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[15].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[15].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[16].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[16].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[16].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[16].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[16].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[16].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[16].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[16].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[16].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[16].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[16].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[17].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[17].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[17].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[17].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[17].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[17].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[17].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[17].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[17].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[17].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[17].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[18].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[18].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[18].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[18].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[18].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[18].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[18].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[18].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[18].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[18].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[18].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[19].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[19].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[19].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[19].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[19].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[19].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[19].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[19].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[19].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[19].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[19].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[20].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[20].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[20].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[20].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[20].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[20].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[20].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[20].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[20].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[20].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[20].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[21].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[21].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[21].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[21].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[21].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[21].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[21].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[21].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[21].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[21].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[21].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[22].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[22].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[22].pull_en |
Yes |
Yes |
T20,T55,T56 |
Yes |
T57,T20,T58 |
OUTPUT |
mio_attr_o[22].pull_select |
Yes |
Yes |
T57,T20,T58 |
Yes |
T57,T20,T58 |
OUTPUT |
mio_attr_o[22].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[22].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[22].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[22].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[22].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[22].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[22].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[23].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[23].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[23].pull_en |
Yes |
Yes |
T20,T55,T56 |
Yes |
T57,T20,T58 |
OUTPUT |
mio_attr_o[23].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[23].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[23].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[23].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[23].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[23].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[23].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[23].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[24].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[24].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[24].pull_en |
Yes |
Yes |
T20,T55,T56 |
Yes |
T57,T20,T58 |
OUTPUT |
mio_attr_o[24].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[24].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[24].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[24].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[24].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[24].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[24].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[24].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[25].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[25].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[25].pull_en |
Yes |
Yes |
T5,T17,T19 |
Yes |
T4,T5,T6 |
OUTPUT |
mio_attr_o[25].pull_select |
Yes |
Yes |
T5,T17,T19 |
Yes |
T4,T5,T6 |
OUTPUT |
mio_attr_o[25].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[25].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[25].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[25].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[25].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[25].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[25].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[26].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[26].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[26].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[26].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[26].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[26].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[26].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[26].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[26].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[26].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[26].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[27].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[27].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[27].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[27].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[27].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[27].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[27].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[27].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[27].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[27].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[27].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[28].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[28].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[28].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[28].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[28].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[28].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[28].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[28].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[28].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[28].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[28].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[29].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[29].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[29].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[29].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[29].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[29].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[29].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[29].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[29].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[29].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[29].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[30].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[30].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[30].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[30].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[30].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[30].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[30].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[30].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[30].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[30].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[30].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[31].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[31].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[31].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[31].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[31].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[31].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[31].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[31].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[31].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[31].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[31].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[32].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[32].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[32].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[32].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[32].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[32].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[32].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[32].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[32].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[32].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[32].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[33].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[33].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[33].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[33].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[33].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[33].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[33].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[33].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[33].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[33].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[33].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[34].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[34].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[34].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[34].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[34].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[34].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[34].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[34].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[34].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[34].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[34].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[35].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[35].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[35].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[35].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[35].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[35].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[35].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[35].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[35].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[35].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[35].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[36].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[36].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[36].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[36].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[36].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[36].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[36].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[36].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[36].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[36].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[36].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[37].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[37].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[37].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[37].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[37].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[37].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[37].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[37].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[37].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[37].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[37].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[38].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[38].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[38].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[38].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[38].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[38].schmitt_en |
Yes |
Yes |
T59,T60,T61 |
Yes |
T62,T59,T60 |
OUTPUT |
mio_attr_o[38].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[38].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[38].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[38].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[38].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[39].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[39].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[39].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[39].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[39].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[39].schmitt_en |
Yes |
Yes |
T59,T60,T61 |
Yes |
T62,T59,T60 |
OUTPUT |
mio_attr_o[39].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[39].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[39].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[39].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[39].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[40].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[40].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[40].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[40].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[40].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[40].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[40].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[40].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[40].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[40].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[40].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[41].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[41].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[41].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[41].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[41].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[41].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[41].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[41].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[41].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[41].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[41].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[42].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[42].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[42].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[42].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[42].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[42].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[42].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[42].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[42].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[42].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[42].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[43].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[43].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[43].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[43].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[43].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[43].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[43].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[43].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[43].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[43].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[43].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[44].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[44].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[44].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[44].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[44].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[44].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[44].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[44].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[44].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[44].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[44].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[45].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[45].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[45].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[45].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[45].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[45].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[45].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[45].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[45].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[45].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[45].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[46].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[46].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[46].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[46].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[46].keep_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[46].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[46].od_en |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[46].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[46].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
mio_attr_o[46].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
mio_attr_o[46].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
mio_out_o[46:0] |
Yes |
Yes |
T30,T39,T40 |
Yes |
T30,T39,T40 |
OUTPUT |
mio_oe_o[46:0] |
Yes |
Yes |
T30,T40,T41 |
Yes |
T30,T39,T40 |
OUTPUT |
mio_in_i[46:0] |
Yes |
Yes |
T28,T29,T30 |
Yes |
T28,T29,T30 |
INPUT |
dio_attr_o[0].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[0].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[0].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[0].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[0].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[0].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[0].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[0].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[0].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[0].drive_strength[0] |
Yes |
Yes |
*T5,*T17,*T19 |
Yes |
T4,T5,T6 |
OUTPUT |
dio_attr_o[0].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[1].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[1].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[1].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[1].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[1].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[1].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[1].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[1].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[1].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[1].drive_strength[0] |
Yes |
Yes |
*T5,*T17,*T19 |
Yes |
T4,T5,T6 |
OUTPUT |
dio_attr_o[1].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[2].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[2].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[2].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T25 |
OUTPUT |
dio_attr_o[2].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T25 |
OUTPUT |
dio_attr_o[2].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[2].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[2].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[2].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[2].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[2].drive_strength[0] |
Yes |
Yes |
*T43,*T44,*T47 |
Yes |
T43,T44,T47 |
OUTPUT |
dio_attr_o[2].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[3].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[3].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[3].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T25 |
OUTPUT |
dio_attr_o[3].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T25 |
OUTPUT |
dio_attr_o[3].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[3].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[3].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[3].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[3].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[3].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[3].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[4].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[4].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[4].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T25 |
OUTPUT |
dio_attr_o[4].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T25 |
OUTPUT |
dio_attr_o[4].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[4].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[4].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[4].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[4].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[4].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[4].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[5].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[5].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[5].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T25 |
OUTPUT |
dio_attr_o[5].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T25 |
OUTPUT |
dio_attr_o[5].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[5].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[5].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[5].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[5].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[5].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[5].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[6].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[6].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[6].pull_en |
Yes |
Yes |
T43,T44,T47 |
Yes |
T43,T44,T47 |
OUTPUT |
dio_attr_o[6].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[6].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[6].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[6].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[6].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[6].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[6].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[6].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[7].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[7].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[7].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[7].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[7].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[7].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[7].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[7].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[7].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[7].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[7].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[8].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[8].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[8].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[8].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[8].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[8].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[8].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[8].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[8].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[8].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[8].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[9].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[9].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[9].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[9].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[9].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[9].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[9].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[9].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[9].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[9].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[9].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[10].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[10].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T49,T50,T51 |
OUTPUT |
dio_attr_o[10].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[10].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[10].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[10].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[10].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[10].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[10].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[10].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[10].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[11].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[11].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T49,T50,T51 |
OUTPUT |
dio_attr_o[11].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[11].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[11].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[11].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[11].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[11].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[11].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[11].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[11].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[12].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[12].virt_od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[12].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[12].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[12].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[12].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[12].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[12].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[12].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[12].drive_strength[3:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[13].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[13].virt_od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[13].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[13].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[13].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[13].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[13].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[13].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[13].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[13].drive_strength[3:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[14].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[14].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[14].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
dio_attr_o[14].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
dio_attr_o[14].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[14].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[14].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[14].input_disable |
Yes |
Yes |
T43,T44,T47 |
Yes |
T43,T44,T47 |
OUTPUT |
dio_attr_o[14].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[14].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[14].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[15].invert |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[15].virt_od_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[15].pull_en |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
dio_attr_o[15].pull_select |
Yes |
Yes |
T42,T43,T44 |
Yes |
T45,T46,T48 |
OUTPUT |
dio_attr_o[15].keep_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[15].schmitt_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[15].od_en |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[15].input_disable |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[15].slew_rate[1:0] |
No |
No |
|
No |
|
OUTPUT |
dio_attr_o[15].drive_strength[0] |
Yes |
Yes |
*T42,*T43,*T44 |
Yes |
T42,T43,T44 |
OUTPUT |
dio_attr_o[15].drive_strength[3:1] |
No |
No |
|
No |
|
OUTPUT |
dio_out_o[11:0] |
Yes |
Yes |
*T31,*T1,*T32 |
Yes |
T31,T33,T2 |
OUTPUT |
dio_out_o[13:12] |
No |
No |
|
No |
|
OUTPUT |
dio_out_o[15:14] |
Yes |
Yes |
T25,T26,T27 |
Yes |
T22,T25,T26 |
OUTPUT |
dio_oe_o[15:0] |
Yes |
Yes |
T31,T37,T38 |
Yes |
T31,T37,T22 |
OUTPUT |
dio_in_i[15:0] |
Yes |
Yes |
T31,T32,T37 |
Yes |
T31,T32,T37 |
INPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
pinmux
| Line No. | Total | Covered | Percent |
Branches |
|
778 |
662 |
85.09 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
2 |
50.00 |
TERNARY |
496 |
4 |
2 |
50.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
2 |
50.00 |
TERNARY |
496 |
4 |
2 |
50.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
2 |
50.00 |
TERNARY |
496 |
4 |
2 |
50.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
2 |
50.00 |
TERNARY |
496 |
4 |
2 |
50.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
2 |
50.00 |
TERNARY |
496 |
4 |
2 |
50.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
4 |
100.00 |
TERNARY |
496 |
4 |
4 |
100.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
2 |
50.00 |
TERNARY |
496 |
4 |
2 |
50.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
479 |
2 |
2 |
100.00 |
TERNARY |
483 |
2 |
2 |
100.00 |
TERNARY |
492 |
4 |
3 |
75.00 |
TERNARY |
496 |
4 |
3 |
75.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
2 |
50.00 |
TERNARY |
532 |
4 |
2 |
50.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
2 |
50.00 |
TERNARY |
532 |
4 |
2 |
50.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
2 |
50.00 |
TERNARY |
532 |
4 |
2 |
50.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
3 |
75.00 |
TERNARY |
532 |
4 |
3 |
75.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
2 |
50.00 |
TERNARY |
532 |
4 |
2 |
50.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
3 |
75.00 |
TERNARY |
532 |
4 |
3 |
75.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
3 |
75.00 |
TERNARY |
532 |
4 |
3 |
75.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
3 |
75.00 |
TERNARY |
532 |
4 |
3 |
75.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
3 |
75.00 |
TERNARY |
532 |
4 |
3 |
75.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
4 |
100.00 |
TERNARY |
532 |
4 |
4 |
100.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
2 |
50.00 |
TERNARY |
532 |
4 |
2 |
50.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
3 |
75.00 |
TERNARY |
532 |
4 |
3 |
75.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
2 |
50.00 |
TERNARY |
532 |
4 |
2 |
50.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
3 |
75.00 |
TERNARY |
532 |
4 |
3 |
75.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
4 |
100.00 |
TERNARY |
532 |
4 |
4 |
100.00 |
TERNARY |
515 |
2 |
2 |
100.00 |
TERNARY |
519 |
2 |
2 |
100.00 |
TERNARY |
528 |
4 |
3 |
75.00 |
TERNARY |
532 |
4 |
3 |
75.00 |
TERNARY |
591 |
2 |
2 |
100.00 |
TERNARY |
591 |
2 |
1 |
50.00 |
TERNARY |
591 |
2 |
2 |
100.00 |
TERNARY |
591 |
2 |
1 |
50.00 |
TERNARY |
591 |
2 |
2 |
100.00 |
TERNARY |
591 |
2 |
2 |
100.00 |
TERNARY |
591 |
2 |
1 |
50.00 |
TERNARY |
591 |
2 |
2 |
100.00 |
IF |
162 |
2 |
2 |
100.00 |
IF |
423 |
2 |
2 |
100.00 |
IF |
553 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[0].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[0].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T24,T15 |
0 |
1 |
- |
Covered |
T22,T13,T14 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T24,T15 |
0 |
1 |
- |
Covered |
T22,T13,T14 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[1].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[1].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T13,T14 |
0 |
1 |
- |
Covered |
T22,T13,T15 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T13,T14 |
0 |
1 |
- |
Covered |
T22,T13,T15 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[2].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[2].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23,T13 |
0 |
1 |
- |
Covered |
T13,T24,T15 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23,T13 |
0 |
1 |
- |
Covered |
T13,T24,T15 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[3].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[3].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T13,T24,T15 |
0 |
1 |
- |
Covered |
T8,T23,T13 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T13,T24,T15 |
0 |
1 |
- |
Covered |
T8,T23,T13 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[4].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[4].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T13,T24 |
0 |
1 |
- |
Covered |
T23,T13,T14 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T13,T24 |
0 |
1 |
- |
Covered |
T23,T13,T14 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[5].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[5].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T13 |
0 |
1 |
- |
Covered |
T13,T24,T15 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T13 |
0 |
1 |
- |
Covered |
T13,T24,T15 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[6].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[6].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T13,T24 |
0 |
1 |
- |
Covered |
T13,T14,T15 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T13,T24 |
0 |
1 |
- |
Covered |
T13,T14,T15 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[7].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[7].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T13 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T13,T24,T15 |
0 |
1 |
- |
Covered |
T23,T13,T14 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T13,T24,T15 |
0 |
1 |
- |
Covered |
T23,T13,T14 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[8].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[8].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[9].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[9].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T8,T22,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T8,T22,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[10].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[10].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T11 |
0 |
1 |
- |
Covered |
T22,T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8,T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T11 |
0 |
1 |
- |
Covered |
T22,T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8,T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[11].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[11].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T24 |
0 |
1 |
- |
Covered |
T22,T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T24 |
0 |
1 |
- |
Covered |
T22,T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[12].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[12].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T23 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T23 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[13].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[13].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T11 |
0 |
1 |
- |
Covered |
T22,T23,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T11 |
0 |
1 |
- |
Covered |
T22,T23,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[14].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[14].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T24 |
0 |
1 |
- |
Covered |
T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8,T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T24 |
0 |
1 |
- |
Covered |
T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8,T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[15].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[15].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T11 |
0 |
1 |
- |
Covered |
T22,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T11 |
0 |
1 |
- |
Covered |
T22,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[16].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[16].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T22,T23,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T22,T23,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[17].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[17].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[18].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[18].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8,T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8,T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[19].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[19].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T22 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T22 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[20].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[20].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22 |
0 |
1 |
- |
Covered |
T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22 |
0 |
1 |
- |
Covered |
T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[21].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[21].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[22].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[22].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T24 |
0 |
1 |
- |
Covered |
T23,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T24 |
0 |
1 |
- |
Covered |
T23,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[23].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[23].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T24 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T24 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[24].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[24].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T11 |
0 |
1 |
- |
Covered |
T22,T23,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T11 |
0 |
1 |
- |
Covered |
T22,T23,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[25].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[25].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23 |
0 |
1 |
- |
Covered |
T22,T24,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23 |
0 |
1 |
- |
Covered |
T22,T24,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[26].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[26].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T24 |
0 |
1 |
- |
Covered |
T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8,T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T24 |
0 |
1 |
- |
Covered |
T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8,T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[27].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[27].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T24 |
0 |
1 |
- |
Covered |
T22 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T24 |
0 |
1 |
- |
Covered |
T22 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[28].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[28].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[29].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[29].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T24 |
0 |
1 |
- |
Covered |
T8,T22,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T24 |
0 |
1 |
- |
Covered |
T8,T22,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[30].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[30].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T23,T11 |
0 |
1 |
- |
Covered |
T22,T24,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T23,T11 |
0 |
1 |
- |
Covered |
T22,T24,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[31].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[31].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T24,T11 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T24,T11 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[32].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[32].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T11 |
0 |
1 |
- |
Covered |
T8,T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T11 |
0 |
1 |
- |
Covered |
T8,T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[33].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[33].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T11 |
0 |
1 |
- |
Covered |
T8,T23,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T11 |
0 |
1 |
- |
Covered |
T8,T23,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[34].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[34].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[35].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[35].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[36].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[36].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T11 |
0 |
1 |
- |
Covered |
T22,T23,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T11 |
0 |
1 |
- |
Covered |
T22,T23,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[37].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[37].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T23,T24,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T23,T24,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[38].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[38].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23,T24 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23,T24 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[39].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[39].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T11 |
0 |
1 |
- |
Covered |
T8,T23,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T11 |
0 |
1 |
- |
Covered |
T8,T23,T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[40].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[40].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T11 |
0 |
1 |
- |
Covered |
T24,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T11 |
0 |
1 |
- |
Covered |
T24,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[41].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[41].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8 |
0 |
1 |
- |
Covered |
T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8 |
0 |
1 |
- |
Covered |
T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[42].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[42].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T23 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T23 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[43].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[43].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T23 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T23 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[44].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[44].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T24 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T24 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[45].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[45].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23,T24 |
0 |
1 |
- |
Covered |
T8 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23,T24 |
0 |
1 |
- |
Covered |
T8 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 479 (reg2hw.mio_pad_sleep_status[46].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 483 (reg2hw.mio_pad_sleep_status[46].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 492 ((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ?
-2-: 492 ((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ?
-3-: 492 ((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T24 |
0 |
1 |
- |
Covered |
T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 496 ((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ?
-2-: 496 ((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ?
-3-: 496 ((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T24 |
0 |
1 |
- |
Covered |
T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[0].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[0].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T23 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T23 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[1].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[1].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T23 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T23 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[2].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[2].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T22,T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T22,T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[3].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[3].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T24 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8,T11 |
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T24 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8,T11 |
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[4].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[4].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T23 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T23 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[5].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[5].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23 |
0 |
1 |
- |
Covered |
T8,T24,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23 |
0 |
1 |
- |
Covered |
T8,T24,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[6].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[6].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T23 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8,T22,T23 |
0 |
1 |
- |
Covered |
T24 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[7].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[7].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T11 |
0 |
1 |
- |
Covered |
T8 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23,T11 |
0 |
1 |
- |
Covered |
T8 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[8].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[8].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23,T24 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23,T24 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[9].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[9].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22 |
0 |
1 |
- |
Covered |
T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22 |
0 |
1 |
- |
Covered |
T23 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[10].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[10].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T24,T11 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T24,T11 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[11].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[11].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T24 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T24 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[12].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[12].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Covered |
T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[13].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[13].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T8 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[14].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[14].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23 |
0 |
1 |
- |
Covered |
T22,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T23 |
0 |
1 |
- |
Covered |
T22,T11 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T11 |
LineNo. Expression
-1-: 515 (reg2hw.dio_pad_sleep_status[15].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 519 (reg2hw.dio_pad_sleep_status[15].q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T23,T24 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 528 ((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ?
-2-: 528 ((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ?
-3-: 528 ((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 532 ((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ?
-2-: 532 ((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ?
-3-: 532 ((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T22,T23 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T8 |
LineNo. Expression
-1-: 591 (reg2hw.wkup_detector[0].miodio.q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T11 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 591 (reg2hw.wkup_detector[1].miodio.q) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 591 (reg2hw.wkup_detector[2].miodio.q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T12 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 591 (reg2hw.wkup_detector[3].miodio.q) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 591 (reg2hw.wkup_detector[4].miodio.q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T11 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 591 (reg2hw.wkup_detector[5].miodio.q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T157,T11 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 591 (reg2hw.wkup_detector[6].miodio.q) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 591 (reg2hw.wkup_detector[7].miodio.q) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T11 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 162 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 423 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 553 if (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i))
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T68,T64,T52 |
Assert Coverage for Module :
pinmux
Assertion Details
AlertsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
AonWkupReqKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1614086 |
1421491 |
0 |
0 |
T4 |
399 |
228 |
0 |
0 |
T5 |
4877 |
4695 |
0 |
0 |
T6 |
401 |
229 |
0 |
0 |
T17 |
791 |
619 |
0 |
0 |
T18 |
1687 |
1513 |
0 |
0 |
T19 |
1515 |
1274 |
0 |
0 |
T31 |
6186 |
6012 |
0 |
0 |
T114 |
1017 |
844 |
0 |
0 |
T142 |
343 |
171 |
0 |
0 |
T165 |
376 |
204 |
0 |
0 |
DftJtagTckKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
DftJtagTmsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
DftJtagTrstKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
DftStrapsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
DioKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
DioOeKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
FpvSecCmBusIntegrity_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
7 |
0 |
0 |
T68 |
146011 |
0 |
0 |
0 |
T73 |
17801 |
0 |
0 |
0 |
T106 |
17293 |
0 |
0 |
0 |
T109 |
144516 |
0 |
0 |
0 |
T117 |
281883 |
0 |
0 |
0 |
T162 |
43467 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T167 |
0 |
1 |
0 |
0 |
T168 |
0 |
1 |
0 |
0 |
T169 |
0 |
1 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
T171 |
0 |
1 |
0 |
0 |
T172 |
17702 |
0 |
0 |
0 |
T173 |
32814 |
0 |
0 |
0 |
T174 |
326381 |
0 |
0 |
0 |
T175 |
29965 |
0 |
0 |
0 |
LcJtagTckKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
LcJtagTmsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
LcJtagTrstKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
MioKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
MioOeKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
PinmuxWkupStable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1614086 |
5279 |
0 |
0 |
T1 |
1285 |
25 |
0 |
0 |
T2 |
0 |
494 |
0 |
0 |
T3 |
0 |
541 |
0 |
0 |
T7 |
0 |
473 |
0 |
0 |
T13 |
0 |
114 |
0 |
0 |
T16 |
0 |
535 |
0 |
0 |
T21 |
1363 |
0 |
0 |
0 |
T34 |
4709 |
0 |
0 |
0 |
T59 |
772 |
0 |
0 |
0 |
T100 |
1477 |
0 |
0 |
0 |
T107 |
1237 |
0 |
0 |
0 |
T137 |
1490 |
0 |
0 |
0 |
T157 |
0 |
624 |
0 |
0 |
T176 |
0 |
23 |
0 |
0 |
T177 |
0 |
537 |
0 |
0 |
T178 |
0 |
601 |
0 |
0 |
T179 |
380 |
0 |
0 |
0 |
T180 |
483 |
0 |
0 |
0 |
T181 |
611 |
0 |
0 |
0 |
PwrMgrStrapSampleOnce0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
1704 |
0 |
0 |
T4 |
23419 |
1 |
0 |
0 |
T5 |
317268 |
9 |
0 |
0 |
T6 |
20606 |
1 |
0 |
0 |
T17 |
69501 |
2 |
0 |
0 |
T18 |
170394 |
1 |
0 |
0 |
T19 |
81370 |
3 |
0 |
0 |
T31 |
713090 |
1 |
0 |
0 |
T114 |
71551 |
2 |
0 |
0 |
T142 |
21364 |
1 |
0 |
0 |
T165 |
16645 |
1 |
0 |
0 |
PwrMgrStrapSampleOnce1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
0 |
0 |
960 |
RvJtagTckKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
RvJtagTmsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
RvJtagTrstKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
TlAReadyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
TlDValidKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127717165 |
127042128 |
0 |
0 |
T4 |
23419 |
22883 |
0 |
0 |
T5 |
317268 |
316672 |
0 |
0 |
T6 |
20606 |
20100 |
0 |
0 |
T17 |
69501 |
68591 |
0 |
0 |
T18 |
170394 |
169992 |
0 |
0 |
T19 |
81370 |
80227 |
0 |
0 |
T31 |
713090 |
712614 |
0 |
0 |
T114 |
71551 |
71070 |
0 |
0 |
T142 |
21364 |
20475 |
0 |
0 |
T165 |
16645 |
16173 |
0 |
0 |
UsbWakeDetectActiveKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1614086 |
1421491 |
0 |
0 |
T4 |
399 |
228 |
0 |
0 |
T5 |
4877 |
4695 |
0 |
0 |
T6 |
401 |
229 |
0 |
0 |
T17 |
791 |
619 |
0 |
0 |
T18 |
1687 |
1513 |
0 |
0 |
T19 |
1515 |
1274 |
0 |
0 |
T31 |
6186 |
6012 |
0 |
0 |
T114 |
1017 |
844 |
0 |
0 |
T142 |
343 |
171 |
0 |
0 |
T165 |
376 |
204 |
0 |
0 |
UsbWkupReqKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1614086 |
1421491 |
0 |
0 |
T4 |
399 |
228 |
0 |
0 |
T5 |
4877 |
4695 |
0 |
0 |
T6 |
401 |
229 |
0 |
0 |
T17 |
791 |
619 |
0 |
0 |
T18 |
1687 |
1513 |
0 |
0 |
T19 |
1515 |
1274 |
0 |
0 |
T31 |
6186 |
6012 |
0 |
0 |
T114 |
1017 |
844 |
0 |
0 |
T142 |
343 |
171 |
0 |
0 |
T165 |
376 |
204 |
0 |
0 |