Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.21 87.21

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_dm 87.21 87.21



Module Instance : tb.dut.top_earlgrey.u_rv_dm

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.21 87.21


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.21 87.21


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.59 90.68 87.09 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : rv_dm
TotalCoveredPercent
Totals 86 56 65.12
Total Bits 938 818 87.21
Total Bits 0->1 469 409 87.21
Total Bits 1->0 469 409 87.21

Ports 86 56 65.12
Port Bits 938 818 87.21
Port Bits 0->1 469 409 87.21
Port Bits 1->0 469 409 87.21

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_lc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
rst_lc_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
next_dm_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
lc_hw_debug_en_i[3:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
lc_dft_en_i[3:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
pinmux_hw_debug_en_i[3:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
otp_dis_rv_dm_late_debug_i[7:0] Yes Yes T4,T5,T6 Yes T5,T17,T19 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
ndmreset_req_o Yes Yes T119,T9,T10 Yes T119,T9,T10 OUTPUT
dmactive_o Yes Yes T61,T64,T8 Yes T61,T117,T63 OUTPUT
debug_req_o Yes Yes T117,T63,T118 Yes T117,T63,T118 OUTPUT
unavailable_i Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.d_ready Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
regs_tl_d_i.a_user.data_intg[6:0] Yes Yes T11,T8 Yes T11,T8 INPUT
regs_tl_d_i.a_user.cmd_intg[0] Yes Yes *T8,*T11 Yes T8,T11 INPUT
regs_tl_d_i.a_user.cmd_intg[1] No No No INPUT
regs_tl_d_i.a_user.cmd_intg[6:2] Yes Yes T8,T11 Yes T8,T11 INPUT
regs_tl_d_i.a_user.instr_type[0] Yes Yes *T8,*T11 Yes T8,T11 INPUT
regs_tl_d_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_d_i.a_user.instr_type[3] Yes Yes T8,T11 Yes T8,T11 INPUT
regs_tl_d_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_data[31:0] Yes Yes T8,T11 Yes T8,T11 INPUT
regs_tl_d_i.a_mask[3:0] Yes Yes T8,T11 Yes T8,T11 INPUT
regs_tl_d_i.a_address[1:0] No No No INPUT
regs_tl_d_i.a_address[3:2] Yes Yes T8,T11 Yes T8,T11 INPUT
regs_tl_d_i.a_address[20:4] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_address[21] Yes Yes *T8,*T11 Yes T8,T11 INPUT
regs_tl_d_i.a_address[23:22] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_address[24] Yes Yes *T8,*T11 Yes T8,T11 INPUT
regs_tl_d_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_address[30] Yes Yes *T8,*T11 Yes T8,T11 INPUT
regs_tl_d_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_source[0] Yes Yes *T8,*T11 Yes T8,T11 INPUT
regs_tl_d_i.a_source[5:1] No No No INPUT
regs_tl_d_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_size[0] No No No INPUT
regs_tl_d_i.a_size[1] Yes Yes T8,T11 Yes T8,T11 INPUT
regs_tl_d_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_opcode[1:0] No No No INPUT
regs_tl_d_i.a_opcode[2] Yes Yes T8,T11 Yes T8,T11 INPUT
regs_tl_d_i.a_valid Yes Yes T8,T11 Yes T8,T11 INPUT
regs_tl_d_o.a_ready Yes Yes T8,T11 Yes T8,T11 OUTPUT
regs_tl_d_o.d_error No No No OUTPUT
regs_tl_d_o.d_user.data_intg[1:0] Yes Yes T11 Yes T11 OUTPUT
regs_tl_d_o.d_user.data_intg[2] No No No OUTPUT
regs_tl_d_o.d_user.data_intg[6:3] Yes Yes T8,T11 Yes T8,T11 OUTPUT
regs_tl_d_o.d_user.rsp_intg[1:0] Yes Yes T8,T11 Yes T8,T11 OUTPUT
regs_tl_d_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:4] Yes Yes T8,T11 Yes T8,T11 OUTPUT
regs_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_d_o.d_data[31:0] Yes Yes T8,T11 Yes T8,T11 OUTPUT
regs_tl_d_o.d_sink No No No OUTPUT
regs_tl_d_o.d_source[0] Yes Yes *T8,*T11 Yes T8,T11 OUTPUT
regs_tl_d_o.d_source[5:1] No No No OUTPUT
regs_tl_d_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_d_o.d_size[0] No No No OUTPUT
regs_tl_d_o.d_size[1] Yes Yes T8,T11 Yes T8,T11 OUTPUT
regs_tl_d_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_d_o.d_opcode[0] Yes Yes *T8,*T11 Yes T8,T11 OUTPUT
regs_tl_d_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_d_o.d_valid Yes Yes T8,T11 Yes T8,T11 OUTPUT
mem_tl_d_i.d_ready Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
mem_tl_d_i.a_user.data_intg[6:0] Yes Yes T117,T63,T8 Yes T117,T63,T8 INPUT
mem_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T117,T63,T8 Yes T117,T63,T8 INPUT
mem_tl_d_i.a_user.instr_type[3:0] Yes Yes T117,T63,T8 Yes T117,T63,T8 INPUT
mem_tl_d_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
mem_tl_d_i.a_data[31:0] Yes Yes T117,T63,T8 Yes T117,T63,T8 INPUT
mem_tl_d_i.a_mask[3:0] Yes Yes T117,T63,T8 Yes T117,T63,T8 INPUT
mem_tl_d_i.a_address[1:0] No No No INPUT
mem_tl_d_i.a_address[11:2] Yes Yes T117,T63,*T8 Yes T117,T63,T8 INPUT
mem_tl_d_i.a_address[15:12] Unreachable Unreachable Unreachable INPUT
mem_tl_d_i.a_address[16] Yes Yes *T117,*T63,*T8 Yes T117,T63,T8 INPUT
mem_tl_d_i.a_address[31:17] Unreachable Unreachable Unreachable INPUT
mem_tl_d_i.a_source[4:0] Yes Yes *T117,*T63,*T118 Yes T117,T63,T118 INPUT
mem_tl_d_i.a_source[5] No No No INPUT
mem_tl_d_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
mem_tl_d_i.a_size[0] No No No INPUT
mem_tl_d_i.a_size[1] Yes Yes T117,T63,T8 Yes T117,T63,T8 INPUT
mem_tl_d_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
mem_tl_d_i.a_opcode[1:0] No No No INPUT
mem_tl_d_i.a_opcode[2] Yes Yes T117,T63,T8 Yes T117,T63,T8 INPUT
mem_tl_d_i.a_valid Yes Yes T117,T63,T8 Yes T117,T63,T8 INPUT
mem_tl_d_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
mem_tl_d_o.d_error Yes Yes T4,T5,T6 Yes T5,T17,T19 OUTPUT
mem_tl_d_o.d_user.data_intg[6:0] Yes Yes T117,T63,T118 Yes T117,T63,T118 OUTPUT
mem_tl_d_o.d_user.rsp_intg[2:0] Yes Yes *T117,*T63,*T8 Yes T117,T63,T8 OUTPUT
mem_tl_d_o.d_user.rsp_intg[3] No No No OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:4] Yes Yes *T8,*T119,*T120 Yes T117,T63,T8 OUTPUT
mem_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
mem_tl_d_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T5,T17,T19 OUTPUT
mem_tl_d_o.d_sink No No No OUTPUT
mem_tl_d_o.d_source[4:0] Yes Yes *T117,*T63,*T118 Yes T117,T63,T118 OUTPUT
mem_tl_d_o.d_source[5] No No No OUTPUT
mem_tl_d_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
mem_tl_d_o.d_size[0] No No No OUTPUT
mem_tl_d_o.d_size[1] Yes Yes T8,T119,T120 Yes T117,T63,T8 OUTPUT
mem_tl_d_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
mem_tl_d_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T5,T17,T19 OUTPUT
mem_tl_d_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
mem_tl_d_o.d_valid Yes Yes T117,T63,T8 Yes T117,T63,T8 OUTPUT
sba_tl_h_o.d_ready Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
sba_tl_h_o.a_user.data_intg[6:0] Yes Yes T63,T64,T116 Yes T63,T64,T116 OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
sba_tl_h_o.a_user.instr_type[0] Yes Yes *T5,*T17,*T19 Yes T4,T5,T6 OUTPUT
sba_tl_h_o.a_user.instr_type[2:1] No No No OUTPUT
sba_tl_h_o.a_user.instr_type[3] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
sba_tl_h_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
sba_tl_h_o.a_data[31:0] Yes Yes T63,T64,T116 Yes T63,T64,T116 OUTPUT
sba_tl_h_o.a_mask[3:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
sba_tl_h_o.a_address[1:0] No No No OUTPUT
sba_tl_h_o.a_address[31:2] Yes Yes T61,T63,T64 Yes T61,T63,T64 OUTPUT
sba_tl_h_o.a_source[5:0] No No No OUTPUT
sba_tl_h_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
sba_tl_h_o.a_size[0] No No No OUTPUT
sba_tl_h_o.a_size[1] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
sba_tl_h_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
sba_tl_h_o.a_opcode[1:0] No No No OUTPUT
sba_tl_h_o.a_opcode[2] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
sba_tl_h_o.a_valid Yes Yes T63,T64,T116 Yes T63,T64,T116 OUTPUT
sba_tl_h_i.a_ready Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
sba_tl_h_i.d_error No No No INPUT
sba_tl_h_i.d_user.data_intg[6:0] Yes Yes T64,T116,T8 Yes T64,T116,T8 INPUT
sba_tl_h_i.d_user.rsp_intg[1:0] Yes Yes T63,T64,T116 Yes T63,T64,T116 INPUT
sba_tl_h_i.d_user.rsp_intg[2] No No No INPUT
sba_tl_h_i.d_user.rsp_intg[5:3] Yes Yes T63,T64,T116 Yes T63,T64,T116 INPUT
sba_tl_h_i.d_user.rsp_intg[6] No No No INPUT
sba_tl_h_i.d_data[31:0] Yes Yes T116,T8,T97 Yes T116,T8,T97 INPUT
sba_tl_h_i.d_sink No No No INPUT
sba_tl_h_i.d_source[5:0] No No No INPUT
sba_tl_h_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
sba_tl_h_i.d_size[0] No No No INPUT
sba_tl_h_i.d_size[1] Yes Yes T63,T64,T116 Yes T63,T64,T116 INPUT
sba_tl_h_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
sba_tl_h_i.d_opcode[0] Yes Yes *T63,*T64,*T116 Yes T63,T64,T116 INPUT
sba_tl_h_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
sba_tl_h_i.d_valid Yes Yes T63,T64,T116 Yes T63,T64,T116 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T110,T163,T278 Yes T110,T163,T278 INPUT
alert_rx_i[0].ping_n Yes Yes T110,T163,T278 Yes T110,T163,T164 INPUT
alert_rx_i[0].ping_p Yes Yes T110,T163,T164 Yes T110,T163,T278 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T110,T163,T278 Yes T110,T163,T278 OUTPUT
jtag_i.tdi Yes Yes T61,T117,T63 Yes T61,T117,T63 INPUT
jtag_i.trst_n Yes Yes T61,T64,T116 Yes T61,T117,T63 INPUT
jtag_i.tms Yes Yes T61,T117,T63 Yes T61,T117,T63 INPUT
jtag_i.tck Yes Yes T61,T117,T63 Yes T61,T117,T63 INPUT
jtag_o.tdo_oe Yes Yes T61,T117,T63 Yes T61,T117,T63 OUTPUT
jtag_o.tdo Yes Yes T61,T117,T63 Yes T61,T117,T63 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%