Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
clk_aon_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T5,T17,T19 |
Yes |
T4,T5,T6 |
INPUT |
rst_aon_ni |
Yes |
Yes |
T5,T17,T19 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[0] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[2:1] |
No |
No |
|
No |
|
INPUT |
tl_i.a_user.instr_type[3] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[1:0] |
No |
No |
|
No |
|
INPUT |
tl_i.a_address[6:2] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[17:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[18] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[21:19] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[22] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:23] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T63,*T64,*T8 |
Yes |
T63,T64,T8 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[0] |
Yes |
Yes |
*T8,*T65,*T66 |
Yes |
T8,T65,T66 |
INPUT |
tl_i.a_opcode[1] |
No |
No |
|
No |
|
INPUT |
tl_i.a_opcode[2] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
OUTPUT |
tl_o.d_error |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
OUTPUT |
tl_o.d_user.rsp_intg[1:0] |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
OUTPUT |
tl_o.d_user.rsp_intg[3:2] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_user.rsp_intg[5:4] |
Yes |
Yes |
*T9,*T10,*T352 |
Yes |
T1,T72,T79 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
OUTPUT |
tl_o.d_sink |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_source[0] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_source[1] |
Yes |
Yes |
*T1,*T72,*T79 |
Yes |
T1,T72,T79 |
OUTPUT |
tl_o.d_source[5:2] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[0] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_size[1] |
Yes |
Yes |
T9,T10,T352 |
Yes |
T1,T72,T79 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T72,*T79 |
Yes |
T1,T72,T79 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T110,T184,T163 |
Yes |
T110,T184,T163 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T110,T184,T163 |
Yes |
T110,T184,T163 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T110,T184,T163 |
Yes |
T110,T184,T163 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T110,T184,T163 |
Yes |
T110,T184,T163 |
OUTPUT |
adc_o.pd |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
OUTPUT |
adc_o.channel_sel[1:0] |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
OUTPUT |
adc_i.data_valid |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
INPUT |
adc_i.data[9:0] |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
INPUT |
intr_match_pending_o |
Yes |
Yes |
T72,T79,T186 |
Yes |
T72,T79,T186 |
OUTPUT |
wkup_req_o |
Yes |
Yes |
T1,T72,T79 |
Yes |
T1,T72,T79 |
OUTPUT |