Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sram_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.73 93.73

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sram_ctrl_main 89.17 89.17
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon 94.19 94.19


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.17 89.17


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.17 89.17


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.59 90.68 87.09 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.19 94.19


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.19 94.19


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.59 90.68 87.09 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : sram_ctrl
TotalCoveredPercent
Totals 66 45 68.18
Total Bits 1164 1091 93.73
Total Bits 0->1 582 546 93.81
Total Bits 1->0 582 545 93.64

Ports 66 45 68.18
Port Bits 1164 1091 93.73
Port Bits 0->1 582 546 93.81
Port Bits 1->0 582 545 93.64

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
ram_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[20:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[27:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_error Yes Yes T4,T5,T6 Yes T5,T17,T19 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_source[5] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T57,T20,T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T57,T20,T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[5:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[17:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T57,*T20,*T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T63,*T64,*T8 Yes T63,T64,T8 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T8,*T65,*T66 Yes T8,T65,T66 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_valid Yes Yes T57,T20,T21 Yes T57,T20,T21 INPUT
regs_tl_o.a_ready Yes Yes T57,T20,T21 Yes T57,T20,T21 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[5:0] Yes Yes *T21,*T153,T155 Yes T21,T153,T155 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T20,T21,T55 Yes T57,T20,T21 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes *T20,T21,*T55 Yes T57,T20,T21 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T20,T21,T55 Yes T57,T20,T21 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[0] No No Yes T63,T118 OUTPUT
regs_tl_o.d_source[1] Yes Yes *T20,*T21,*T55 Yes T57,T20,T21 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T20,T21,T55 Yes T57,T20,T21 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T21,*T153,*T155 Yes T21,T151,T152 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T57,T20,T21 Yes T57,T20,T21 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T110,T184,T152 Yes T110,T184,T152 INPUT
alert_rx_i[0].ping_n Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_rx_i[0].ping_p Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T110,T184,T152 Yes T110,T184,T152 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T5,T17,T114 Yes T5,T17,T114 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T4,T5,T6 Yes T5,T17,T19 INPUT
sram_otp_key_o.req Yes Yes T57,T20,T58 Yes T57,T20,T58 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i.key[127:0] Yes Yes T4,T5,T6 Yes T5,T6,T17 INPUT
sram_otp_key_i.ack Yes Yes T57,T20,T58 Yes T57,T20,T58 INPUT
cfg_i.rf_cfg.cfg[3:0] No No No INPUT
cfg_i.rf_cfg.cfg_en No No No INPUT
cfg_i.rf_cfg.test No No No INPUT
cfg_i.ram_cfg.cfg[3:0] No No No INPUT
cfg_i.ram_cfg.cfg_en No No No INPUT
cfg_i.ram_cfg.test No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main
TotalCoveredPercent
Totals 62 39 62.90
Total Bits 1136 1013 89.17
Total Bits 0->1 568 507 89.26
Total Bits 1->0 568 506 89.08

Ports 62 39 62.90
Port Bits 1136 1013 89.17
Port Bits 0->1 568 507 89.26
Port Bits 1->0 568 506 89.08

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
ram_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[27:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[31:29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_source[5] No No No INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[0] No No No INPUT
ram_tl_i.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_error Yes Yes T4,T5,T6 Yes T5,T17,T19 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_source[5] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T57,T20,T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_user.cmd_intg[0] Yes Yes *T57,*T20,*T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_user.cmd_intg[1] No No No INPUT
regs_tl_i.a_user.cmd_intg[6:2] Yes Yes T21,T151,T152 Yes T21,T151,T152 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T57,*T20,*T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T57,T20,T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[4:0] Yes Yes *T57,*T20,*T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_data[6:5] No No No INPUT
regs_tl_i.a_data[7] Yes Yes *T57,*T20,*T58 Yes T57,T20,T58 INPUT
regs_tl_i.a_data[31:8] No No No INPUT
regs_tl_i.a_mask[3:0] Yes Yes T57,T20,T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[5:2] Yes Yes *T57,*T20,*T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_address[17:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T57,T20,T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T57,*T20,*T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T57,*T20,*T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[1:0] Yes Yes *T63,*T118,*T57 Yes T63,T118,T57 INPUT
regs_tl_i.a_source[5:2] No No No INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[0] No No No INPUT
regs_tl_i.a_size[1] Yes Yes T57,T20,T21 Yes T57,T20,T21 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[1:0] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T21,T151,T152 Yes T21,T151,T152 INPUT
regs_tl_i.a_valid Yes Yes T57,T20,T21 Yes T57,T20,T21 INPUT
regs_tl_o.a_ready Yes Yes T57,T20,T21 Yes T57,T20,T21 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[5:0] Yes Yes *T21,*T153,*T154 Yes T21,T153,T154 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T20,T21,T55 Yes T57,T20,T21 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes *T20,T21,*T55 Yes T57,T20,T21 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T20,T21,T55 Yes T57,T20,T21 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[0] No No Yes T63,T118 OUTPUT
regs_tl_o.d_source[1] Yes Yes *T20,*T21,*T55 Yes T57,T20,T21 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T20,T21,T55 Yes T57,T20,T21 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T21,*T153,*T155 Yes T21,T151,T152 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T57,T20,T21 Yes T57,T20,T21 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T110,T152,T163 Yes T110,T152,T163 INPUT
alert_rx_i[0].ping_n Yes Yes T110,T163,T164 Yes T110,T163,T164 INPUT
alert_rx_i[0].ping_p Yes Yes T110,T163,T164 Yes T110,T163,T164 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T110,T152,T163 Yes T110,T152,T163 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T5,T17,T114 Yes T5,T17,T114 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T4,T5,T6 Yes T5,T17,T19 INPUT
sram_otp_key_o.req Yes Yes T57,T20,T58 Yes T57,T20,T58 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i.key[127:0] Yes Yes T4,T5,T6 Yes T5,T6,T17 INPUT
sram_otp_key_i.ack Yes Yes T57,T20,T58 Yes T57,T20,T58 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test No No No INPUT
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon
TotalCoveredPercent
Totals 60 42 70.00
Total Bits 1102 1038 94.19
Total Bits 0->1 551 519 94.19
Total Bits 1->0 551 519 94.19

Ports 60 42 70.00
Port Bits 1102 1038 94.19
Port Bits 0->1 551 519 94.19
Port Bits 1->0 551 519 94.19

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
ram_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T5,T17,T19 Yes T5,T17,T19 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[2:1] No No No INPUT
ram_tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[11:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[20:12] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T63,*T64,*T8 Yes T63,T64,T8 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T8,*T65,*T66 Yes T8,T65,T66 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_error Yes Yes T4,T5,T6 Yes T5,T17,T19 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T5,T17,T19 Yes T5,T17,T19 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T5,T17,T19 Yes T5,T17,T19 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[1:0] Yes Yes *T65,*T66,*T150 Yes T65,T66,T150 OUTPUT
ram_tl_o.d_source[5:2] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T57,T20,T58 Yes T57,T20,T58 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T57,T20,T58 Yes T57,T20,T58 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[5:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[19:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T63,*T64,*T8 Yes T63,T64,T8 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T8,*T65,*T66 Yes T8,T65,T66 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_valid Yes Yes T57,T20,T58 Yes T57,T20,T58 INPUT
regs_tl_o.a_ready Yes Yes T57,T20,T58 Yes T57,T20,T58 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[5:0] Yes Yes *T155,*T76,T216 Yes T155,T76,T216 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T20,T55,T56 Yes T57,T20,T58 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes *T20,*T55,*T56 Yes T57,T20,T58 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T20,T55,T56 Yes T57,T20,T58 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[0] No No No OUTPUT
regs_tl_o.d_source[1] Yes Yes *T20,*T55,*T56 Yes T57,T20,T58 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T20,T55,T56 Yes T57,T20,T58 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T155,*T76,*T216 Yes T151,T155,T351 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T57,T20,T58 Yes T57,T20,T58 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_rx_i[0].ping_n Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_rx_i[0].ping_p Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T110,T184,T163 Yes T110,T184,T163 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T5,T17,T114 Yes T5,T17,T114 INPUT
lc_hw_debug_en_i[3:0] Unreachable Unreachable Unreachable INPUT
otp_en_sram_ifetch_i[7:0] Unreachable Unreachable Unreachable INPUT
sram_otp_key_o.req Yes Yes T155,T76,T216 Yes T155,T76,T216 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i.key[127:0] Yes Yes T4,T5,T6 Yes T5,T6,T17 INPUT
sram_otp_key_i.ack Yes Yes T155,T76,T216 Yes T155,T76,T216 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test No No No INPUT
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test No No No INPUT

*Tests covering at least one bit in the range
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