Module Definition
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Module : aon_timer
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.13 90.13

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_aon_timer_aon 90.13 90.13



Module Instance : tb.dut.top_earlgrey.u_aon_timer_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.13 90.13


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.13 90.13


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.59 90.68 87.09 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : aon_timer
TotalCoveredPercent
Totals 38 30 78.95
Total Bits 314 283 90.13
Total Bits 0->1 157 142 90.45
Total Bits 1->0 157 141 89.81

Ports 38 30 78.95
Port Bits 314 283 90.13
Port Bits 0->1 157 142 90.45
Port Bits 1->0 157 141 89.81

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
rst_aon_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T5,T17,T114 Yes T5,T17,T114 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T5,T17,T114 Yes T5,T17,T114 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[5:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[21:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T63,*T64,*T8 Yes T63,T64,T8 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T8,*T65,*T66 Yes T8,T65,T66 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_valid Yes Yes T5,T17,T114 Yes T5,T17,T114 INPUT
tl_o.a_ready Yes Yes T5,T17,T114 Yes T5,T17,T114 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T5,T17,T114 Yes T5,T17,T114 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T5,T17,T114 Yes T5,T17,T114 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T5,T17,T114 Yes T5,T17,T114 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T17,T114 Yes T5,T17,T114 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No Yes T63 OUTPUT
tl_o.d_source[1] Yes Yes *T5,*T17,*T114 Yes T5,T17,T114 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T5,T17,T114 Yes T5,T17,T114 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T5,*T17,*T114 Yes T5,T17,T114 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T17,T114 Yes T5,T17,T114 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T342,T110,T163 Yes T342,T110,T163 INPUT
alert_rx_i[0].ping_n Yes Yes T110,T163,T164 Yes T110,T163,T164 INPUT
alert_rx_i[0].ping_p Yes Yes T110,T163,T164 Yes T110,T163,T164 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T342,T110,T163 Yes T342,T110,T163 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T5,T17,T114 Yes T5,T17,T114 INPUT
intr_wkup_timer_expired_o Yes Yes T180,T181,T190 Yes T1,T180,T181 OUTPUT
intr_wdog_timer_bark_o Yes Yes T5,T290,T238 Yes T5,T290,T238 OUTPUT
nmi_wdog_timer_bark_o Yes Yes T5,T290,T238 Yes T5,T290,T238 OUTPUT
wkup_req_o Yes Yes T5,T1,T181 Yes T5,T1,T180 OUTPUT
aon_timer_rst_req_o Yes Yes T5,T238,T354 Yes T5,T238,T354 OUTPUT
sleep_mode_i Yes Yes T4,T5,T6 Yes T5,T19,T20 INPUT

*Tests covering at least one bit in the range
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