Module Definition
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Module : pattgen
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pattgen_0.1/rtl/pattgen.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pattgen 90.00 90.00



Module Instance : tb.dut.top_earlgrey.u_pattgen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.59 90.68 87.09 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : pattgen
TotalCoveredPercent
Totals 35 27 77.14
Total Bits 300 270 90.00
Total Bits 0->1 150 135 90.00
Total Bits 1->0 150 135 90.00

Ports 35 27 77.14
Port Bits 300 270 90.00
Port Bits 0->1 150 135 90.00
Port Bits 1->0 150 135 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T271,T111,T349 Yes T271,T111,T349 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T271,T111,T349 Yes T271,T111,T349 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[5:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[16:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19:17] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T63,*T64,*T8 Yes T63,T64,T8 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T8,*T65,*T66 Yes T8,T65,T66 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_valid Yes Yes T271,T121,T111 Yes T271,T121,T111 INPUT
tl_o.a_ready Yes Yes T271,T121,T111 Yes T271,T121,T111 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T271,T111,T349 Yes T271,T111,T349 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T271,T111,T349 Yes T271,T121,T111 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T139,*T271,*T111 Yes T271,T121,T111 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T271,T111,T349 Yes T271,T121,T111 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T139,*T271,*T111 Yes T139,T271,T111 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T139 Yes T271,T121,T111 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T271,*T111,*T349 Yes T271,T111,T349 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T271,T121,T111 Yes T271,T121,T111 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_rx_i[0].ping_n Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_rx_i[0].ping_p Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T110,T184,T163 Yes T110,T184,T163 OUTPUT
cio_pda0_tx_o Yes Yes T271,T349,T353 Yes T271,T349,T353 OUTPUT
cio_pcl0_tx_o Yes Yes T271,T349,T353 Yes T271,T349,T353 OUTPUT
cio_pda1_tx_o Yes Yes T353,T139 Yes T353,T139 OUTPUT
cio_pcl1_tx_o Yes Yes T353 Yes T353 OUTPUT
cio_pda0_tx_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pcl0_tx_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pda1_tx_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pcl1_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_done_ch0_o Yes Yes T271,T111,T349 Yes T271,T111,T349 OUTPUT
intr_done_ch1_o Yes Yes T111,T353,T112 Yes T111,T353,T112 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%