Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	90.13			90.13
tb.dut.top_earlgrey.u_uart1	90.20			90.20
tb.dut.top_earlgrey.u_uart2	90.20			90.20
tb.dut.top_earlgrey.u_uart3	90.26			90.26

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	278	90.26
Total Bits 0->1	154	139	90.26
Total Bits 1->0	154	139	90.26

Ports	40	32	80.00
Port Bits	308	278	90.26
Port Bits 0->1	154	139	90.26
Port Bits 1->0	154	139	90.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T17,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T8	Yes	T63,T64,T8	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T8,*T65,*T66	Yes	T8,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	INPUT
tl_o.a_ready	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T20,*T109,T55	Yes	T18,T57,T20	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T8,*T18,*T57	Yes	T8,T18,T57	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T20,T109,T55	Yes	T18,T57,T20	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T57,*T20	Yes	T18,T57,T20	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T109,T110,T184	Yes	T109,T110,T184	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T110,T184,T163	Yes	T110,T184,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T110,T184,T163	Yes	T110,T184,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T109,T110,T184	Yes	T109,T110,T184	OUTPUT
cio_rx_i	Yes	Yes	T5,T17,T18	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T18,T100,T268	Yes	T18,T100,T268	OUTPUT
intr_tx_empty_o	Yes	Yes	T18,T100,T268	Yes	T18,T100,T268	OUTPUT
intr_rx_watermark_o	Yes	Yes	T18,T100,T268	Yes	T18,T100,T268	OUTPUT
intr_tx_done_o	Yes	Yes	T18,T100,T268	Yes	T18,T100,T268	OUTPUT
intr_rx_overflow_o	Yes	Yes	T18,T100,T268	Yes	T18,T100,T268	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	40	32	80.00
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T17,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T8	Yes	T63,T64,T8	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T8,*T65,*T66	Yes	T8,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	INPUT
tl_o.a_ready	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T20,*T109,T55	Yes	T18,T57,T20	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T8,*T18,*T57	Yes	T8,T18,T57	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T20,T109,T55	Yes	T18,T57,T20	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T57,*T20	Yes	T18,T57,T20	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T109,T110,T355	Yes	T109,T110,T355	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T110,T163,T164	Yes	T110,T163,T164	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T110,T163,T164	Yes	T110,T163,T164	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T109,T110,T355	Yes	T109,T110,T355	OUTPUT
cio_rx_i	Yes	Yes	T5,T17,T18	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T18,T57,T20	Yes	T18,T57,T20	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T18,T266,T267	Yes	T18,T266,T267	OUTPUT
intr_tx_empty_o	Yes	Yes	T18,T266,T267	Yes	T18,T266,T267	OUTPUT
intr_rx_watermark_o	Yes	Yes	T18,T266,T267	Yes	T18,T266,T267	OUTPUT
intr_tx_done_o	Yes	Yes	T18,T266,T267	Yes	T18,T266,T267	OUTPUT
intr_rx_overflow_o	Yes	Yes	T18,T266,T267	Yes	T18,T266,T267	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	40	32	80.00
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T17,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T268,T269,T130	Yes	T268,T269,T130	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T268,T269,T130	Yes	T268,T269,T130	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T8	Yes	T63,T64,T8	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T8,*T65,*T66	Yes	T8,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T268,T109,T269	Yes	T268,T109,T269	INPUT
tl_o.a_ready	Yes	Yes	T268,T109,T269	Yes	T268,T109,T269	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T268,T269,T130	Yes	T268,T269,T130	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T268,T109,T269	Yes	T268,T109,T269	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T109,T8,*T348	Yes	T268,T109,T269	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T268,T109,T269	Yes	T268,T109,T269	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T8,*T268,*T269	Yes	T8,T268,T269	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T109,T8,T348	Yes	T268,T109,T269	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T268,*T269,*T130	Yes	T268,T269,T130	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T268,T109,T269	Yes	T268,T109,T269	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T109,T110,T163	Yes	T109,T110,T163	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T110,T163,T164	Yes	T110,T163,T164	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T110,T163,T164	Yes	T110,T163,T164	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T109,T110,T163	Yes	T109,T110,T163	OUTPUT
cio_rx_i	Yes	Yes	T268,T269,T333	Yes	T268,T269,T333	INPUT
cio_tx_o	Yes	Yes	T268,T269,T8	Yes	T268,T269,T8	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T268,T269,T130	Yes	T268,T269,T130	OUTPUT
intr_tx_empty_o	Yes	Yes	T268,T269,T130	Yes	T268,T269,T130	OUTPUT
intr_rx_watermark_o	Yes	Yes	T268,T269,T130	Yes	T268,T269,T130	OUTPUT
intr_tx_done_o	Yes	Yes	T268,T269,T130	Yes	T268,T269,T130	OUTPUT
intr_rx_overflow_o	Yes	Yes	T268,T269,T130	Yes	T268,T269,T130	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	40	32	80.00
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T17,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T100,T130,T191	Yes	T100,T130,T191	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T100,T130,T191	Yes	T100,T130,T191	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T8	Yes	T63,T64,T8	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T8,*T65,*T66	Yes	T8,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T100,T109,T130	Yes	T100,T109,T130	INPUT
tl_o.a_ready	Yes	Yes	T100,T109,T130	Yes	T100,T109,T130	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T100,T130,T191	Yes	T100,T130,T191	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T100,T109,T130	Yes	T100,T109,T130	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T109,T8,*T348	Yes	T100,T109,T130	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T100,T109,T130	Yes	T100,T109,T130	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T8,*T100,*T130	Yes	T8,T100,T130	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T109,T8,T348	Yes	T100,T109,T130	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T100,*T130,*T191	Yes	T100,T130,T191	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T100,T109,T130	Yes	T100,T109,T130	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T109,T110,T8	Yes	T109,T110,T8	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T110,T163,T164	Yes	T110,T163,T164	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T110,T163,T164	Yes	T110,T163,T164	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T109,T110,T8	Yes	T109,T110,T8	OUTPUT
cio_rx_i	Yes	Yes	T100,T101,T356	Yes	T100,T101,T356	INPUT
cio_tx_o	Yes	Yes	T100,T101,T356	Yes	T100,T101,T356	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T100,T130,T191	Yes	T100,T130,T191	OUTPUT
intr_tx_empty_o	Yes	Yes	T100,T130,T191	Yes	T100,T130,T191	OUTPUT
intr_rx_watermark_o	Yes	Yes	T100,T130,T191	Yes	T100,T130,T191	OUTPUT
intr_tx_done_o	Yes	Yes	T100,T130,T191	Yes	T100,T130,T191	OUTPUT
intr_rx_overflow_o	Yes	Yes	T100,T130,T191	Yes	T100,T130,T191	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	278	90.26
Total Bits 0->1	154	139	90.26
Total Bits 1->0	154	139	90.26

Ports	40	32	80.00
Port Bits	308	278	90.26
Port Bits 0->1	154	139	90.26
Port Bits 1->0	154	139	90.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T17,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T28,T130,T191	Yes	T28,T130,T191	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T28,T130,T191	Yes	T28,T130,T191	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T8	Yes	T63,T64,T8	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T8,*T65,*T66	Yes	T8,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T28,T109,T130	Yes	T28,T109,T130	INPUT
tl_o.a_ready	Yes	Yes	T28,T109,T130	Yes	T28,T109,T130	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T28,T130,T191	Yes	T28,T130,T191	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T28,T109,T130	Yes	T28,T109,T130	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T109,T8,*T348	Yes	T28,T109,T130	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T28,T109,T130	Yes	T28,T109,T130	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T8,*T28,*T130	Yes	T8,T28,T130	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T109,T8,T348	Yes	T28,T109,T130	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T28,*T130,*T191	Yes	T28,T130,T191	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T28,T109,T130	Yes	T28,T109,T130	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T109,T110,T184	Yes	T109,T110,T184	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T110,T184,T163	Yes	T110,T184,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T110,T184,T163	Yes	T110,T184,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T109,T110,T184	Yes	T109,T110,T184	OUTPUT
cio_rx_i	Yes	Yes	T28,T29,T357	Yes	T28,T29,T357	INPUT
cio_tx_o	Yes	Yes	T28,T29,T8	Yes	T28,T29,T8	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T28,T130,T191	Yes	T28,T130,T191	OUTPUT
intr_tx_empty_o	Yes	Yes	T28,T130,T191	Yes	T28,T130,T191	OUTPUT
intr_rx_watermark_o	Yes	Yes	T28,T130,T191	Yes	T28,T130,T191	OUTPUT
intr_tx_done_o	Yes	Yes	T28,T130,T191	Yes	T28,T130,T191	OUTPUT
intr_rx_overflow_o	Yes	Yes	T28,T130,T191	Yes	T28,T130,T191	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T130,T191,T192	Yes	T130,T191,T192	OUTPUT

*Tests covering at least one bit in the range