Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.88 100.00 86.67 100.00 92.86


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.88 100.00 86.67 100.00 92.86


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ibus_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.88 100.00 86.67 100.00 92.86


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.88 100.00 86.67 100.00 92.86


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_dbus_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
ALWAYS10566100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 2 2
87 2 2
89 2 2
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
121 1 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Module : prim_arbiter_fixed
TotalCoveredPercent
Conditions151386.67
Logical151386.67
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT6,T179,T8
01CoveredT6,T179,T8
10Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT6,T179,T217
1CoveredT6,T179,T8

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT6,T179,T217
1CoveredT6,T179,T8

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Not Covered
10CoveredT6,T179,T8
11CoveredT6,T179,T217

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT6,T179,T8
10CoveredT6,T179,T217
11CoveredT6,T179,T8

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11CoveredT6,T179,T8

Branch Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T6,T179,T8
0 Covered T6,T179,T217


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T6,T179,T8
0 Covered T6,T179,T217


Assert Coverage for Module : prim_arbiter_fixed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 13 92.86
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 13 92.86




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 1017064792 998975462 0 0
CheckNGreaterZero_A 2012 2012 0 0
GntImpliesReady_A 1017064792 8387 0 0
GntImpliesValid_A 1017064792 8387 0 0
GrantKnown_A 1017064792 998975462 0 0
IdxKnown_A 1017064792 998975462 0 0
IndexIsCorrect_A 1017064792 8387 0 0
NoReadyValidNoGrant_A 1017064792 0 0 0
Priority_A 1017064792 8387 0 0
ReadyAndValidImplyGrant_A 1017064792 8387 0 0
ReqAndReadyImplyGrant_A 1017064792 8387 0 0
ReqImpliesValid_A 1017064792 8387 0 0
ValidKnown_A 1017064792 998975462 0 0
gen_data_port_assertion.DataFlow_A 1017064792 8387 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 998975462 0 0
T4 187612 187510 0 0
T5 231184 231066 0 0
T6 164418 164316 0 0
T17 565394 565190 0 0
T18 779240 779116 0 0
T19 645188 644724 0 0
T31 593502 593490 0 0
T114 586064 585846 0 0
T142 167544 167442 0 0
T165 131696 131594 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2012 2012 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0
T19 2 2 0 0
T31 2 2 0 0
T114 2 2 0 0
T142 2 2 0 0
T165 2 2 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 8387 0 0
T6 164418 2794 0 0
T17 565394 0 0 0
T18 779240 0 0 0
T19 645188 0 0 0
T31 593502 0 0 0
T57 301360 0 0 0
T114 586064 0 0 0
T136 924966 0 0 0
T142 167544 0 0 0
T165 131696 0 0 0
T179 0 2795 0 0
T217 0 2798 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 8387 0 0
T6 164418 2794 0 0
T17 565394 0 0 0
T18 779240 0 0 0
T19 645188 0 0 0
T31 593502 0 0 0
T57 301360 0 0 0
T114 586064 0 0 0
T136 924966 0 0 0
T142 167544 0 0 0
T165 131696 0 0 0
T179 0 2795 0 0
T217 0 2798 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 998975462 0 0
T4 187612 187510 0 0
T5 231184 231066 0 0
T6 164418 164316 0 0
T17 565394 565190 0 0
T18 779240 779116 0 0
T19 645188 644724 0 0
T31 593502 593490 0 0
T114 586064 585846 0 0
T142 167544 167442 0 0
T165 131696 131594 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 998975462 0 0
T4 187612 187510 0 0
T5 231184 231066 0 0
T6 164418 164316 0 0
T17 565394 565190 0 0
T18 779240 779116 0 0
T19 645188 644724 0 0
T31 593502 593490 0 0
T114 586064 585846 0 0
T142 167544 167442 0 0
T165 131696 131594 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 8387 0 0
T6 164418 2794 0 0
T17 565394 0 0 0
T18 779240 0 0 0
T19 645188 0 0 0
T31 593502 0 0 0
T57 301360 0 0 0
T114 586064 0 0 0
T136 924966 0 0 0
T142 167544 0 0 0
T165 131696 0 0 0
T179 0 2795 0 0
T217 0 2798 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 0 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 8387 0 0
T6 164418 2794 0 0
T17 565394 0 0 0
T18 779240 0 0 0
T19 645188 0 0 0
T31 593502 0 0 0
T57 301360 0 0 0
T114 586064 0 0 0
T136 924966 0 0 0
T142 167544 0 0 0
T165 131696 0 0 0
T179 0 2795 0 0
T217 0 2798 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 8387 0 0
T6 164418 2794 0 0
T17 565394 0 0 0
T18 779240 0 0 0
T19 645188 0 0 0
T31 593502 0 0 0
T57 301360 0 0 0
T114 586064 0 0 0
T136 924966 0 0 0
T142 167544 0 0 0
T165 131696 0 0 0
T179 0 2795 0 0
T217 0 2798 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 8387 0 0
T6 164418 2794 0 0
T17 565394 0 0 0
T18 779240 0 0 0
T19 645188 0 0 0
T31 593502 0 0 0
T57 301360 0 0 0
T114 586064 0 0 0
T136 924966 0 0 0
T142 167544 0 0 0
T165 131696 0 0 0
T179 0 2795 0 0
T217 0 2798 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 8387 0 0
T6 164418 2794 0 0
T17 565394 0 0 0
T18 779240 0 0 0
T19 645188 0 0 0
T31 593502 0 0 0
T57 301360 0 0 0
T114 586064 0 0 0
T136 924966 0 0 0
T142 167544 0 0 0
T165 131696 0 0 0
T179 0 2795 0 0
T217 0 2798 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 998975462 0 0
T4 187612 187510 0 0
T5 231184 231066 0 0
T6 164418 164316 0 0
T17 565394 565190 0 0
T18 779240 779116 0 0
T19 645188 644724 0 0
T31 593502 593490 0 0
T114 586064 585846 0 0
T142 167544 167442 0 0
T165 131696 131594 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017064792 8387 0 0
T6 164418 2794 0 0
T17 565394 0 0 0
T18 779240 0 0 0
T19 645188 0 0 0
T31 593502 0 0 0
T57 301360 0 0 0
T114 586064 0 0 0
T136 924966 0 0 0
T142 167544 0 0 0
T165 131696 0 0 0
T179 0 2795 0 0
T217 0 2798 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
ALWAYS10566100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 2 2
87 2 2
89 2 2
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
121 1 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region
TotalCoveredPercent
Conditions151386.67
Logical151386.67
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT6,T179,T8
01CoveredT6,T179,T217
10Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT6,T179,T217
1CoveredT6,T179,T8

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT6,T179,T217
1CoveredT6,T179,T8

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Not Covered
10CoveredT6,T179,T217
11CoveredT6,T179,T217

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT6,T179,T8
10CoveredT6,T179,T217
11CoveredT6,T179,T217

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11CoveredT6,T179,T217

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T6,T179,T8
0 Covered T6,T179,T217


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T6,T179,T8
0 Covered T6,T179,T217


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 13 92.86
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 13 92.86




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 508532396 499487731 0 0
CheckNGreaterZero_A 1006 1006 0 0
GntImpliesReady_A 508532396 5196 0 0
GntImpliesValid_A 508532396 5196 0 0
GrantKnown_A 508532396 499487731 0 0
IdxKnown_A 508532396 499487731 0 0
IndexIsCorrect_A 508532396 5196 0 0
NoReadyValidNoGrant_A 508532396 0 0 0
Priority_A 508532396 5196 0 0
ReadyAndValidImplyGrant_A 508532396 5196 0 0
ReqAndReadyImplyGrant_A 508532396 5196 0 0
ReqImpliesValid_A 508532396 5196 0 0
ValidKnown_A 508532396 499487731 0 0
gen_data_port_assertion.DataFlow_A 508532396 5196 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 499487731 0 0
T4 93806 93755 0 0
T5 115592 115533 0 0
T6 82209 82158 0 0
T17 282697 282595 0 0
T18 389620 389558 0 0
T19 322594 322362 0 0
T31 296751 296745 0 0
T114 293032 292923 0 0
T142 83772 83721 0 0
T165 65848 65797 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1006 1006 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T31 1 1 0 0
T114 1 1 0 0
T142 1 1 0 0
T165 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 5196 0 0
T6 82209 1730 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1732 0 0
T217 0 1734 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 5196 0 0
T6 82209 1730 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1732 0 0
T217 0 1734 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 499487731 0 0
T4 93806 93755 0 0
T5 115592 115533 0 0
T6 82209 82158 0 0
T17 282697 282595 0 0
T18 389620 389558 0 0
T19 322594 322362 0 0
T31 296751 296745 0 0
T114 293032 292923 0 0
T142 83772 83721 0 0
T165 65848 65797 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 499487731 0 0
T4 93806 93755 0 0
T5 115592 115533 0 0
T6 82209 82158 0 0
T17 282697 282595 0 0
T18 389620 389558 0 0
T19 322594 322362 0 0
T31 296751 296745 0 0
T114 293032 292923 0 0
T142 83772 83721 0 0
T165 65848 65797 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 5196 0 0
T6 82209 1730 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1732 0 0
T217 0 1734 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 0 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 5196 0 0
T6 82209 1730 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1732 0 0
T217 0 1734 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 5196 0 0
T6 82209 1730 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1732 0 0
T217 0 1734 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 5196 0 0
T6 82209 1730 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1732 0 0
T217 0 1734 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 5196 0 0
T6 82209 1730 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1732 0 0
T217 0 1734 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 499487731 0 0
T4 93806 93755 0 0
T5 115592 115533 0 0
T6 82209 82158 0 0
T17 282697 282595 0 0
T18 389620 389558 0 0
T19 322594 322362 0 0
T31 296751 296745 0 0
T114 293032 292923 0 0
T142 83772 83721 0 0
T165 65848 65797 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 5196 0 0
T6 82209 1730 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1732 0 0
T217 0 1734 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
ALWAYS10566100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 2 2
87 2 2
89 2 2
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
121 1 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region
TotalCoveredPercent
Conditions151386.67
Logical151386.67
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT6,T179,T8
01CoveredT6,T179,T8
10Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT6,T179,T217
1CoveredT6,T179,T8

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT6,T179,T217
1CoveredT6,T179,T8

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Not Covered
10CoveredT6,T179,T8
11CoveredT6,T179,T217

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT6,T179,T8
10CoveredT6,T179,T217
11CoveredT6,T179,T8

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11CoveredT6,T179,T8

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T6,T179,T8
0 Covered T6,T179,T217


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T6,T179,T8
0 Covered T6,T179,T217


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 13 92.86
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 13 92.86




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 508532396 499487731 0 0
CheckNGreaterZero_A 1006 1006 0 0
GntImpliesReady_A 508532396 3191 0 0
GntImpliesValid_A 508532396 3191 0 0
GrantKnown_A 508532396 499487731 0 0
IdxKnown_A 508532396 499487731 0 0
IndexIsCorrect_A 508532396 3191 0 0
NoReadyValidNoGrant_A 508532396 0 0 0
Priority_A 508532396 3191 0 0
ReadyAndValidImplyGrant_A 508532396 3191 0 0
ReqAndReadyImplyGrant_A 508532396 3191 0 0
ReqImpliesValid_A 508532396 3191 0 0
ValidKnown_A 508532396 499487731 0 0
gen_data_port_assertion.DataFlow_A 508532396 3191 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 499487731 0 0
T4 93806 93755 0 0
T5 115592 115533 0 0
T6 82209 82158 0 0
T17 282697 282595 0 0
T18 389620 389558 0 0
T19 322594 322362 0 0
T31 296751 296745 0 0
T114 293032 292923 0 0
T142 83772 83721 0 0
T165 65848 65797 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1006 1006 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T31 1 1 0 0
T114 1 1 0 0
T142 1 1 0 0
T165 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 3191 0 0
T6 82209 1064 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1063 0 0
T217 0 1064 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 3191 0 0
T6 82209 1064 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1063 0 0
T217 0 1064 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 499487731 0 0
T4 93806 93755 0 0
T5 115592 115533 0 0
T6 82209 82158 0 0
T17 282697 282595 0 0
T18 389620 389558 0 0
T19 322594 322362 0 0
T31 296751 296745 0 0
T114 293032 292923 0 0
T142 83772 83721 0 0
T165 65848 65797 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 499487731 0 0
T4 93806 93755 0 0
T5 115592 115533 0 0
T6 82209 82158 0 0
T17 282697 282595 0 0
T18 389620 389558 0 0
T19 322594 322362 0 0
T31 296751 296745 0 0
T114 293032 292923 0 0
T142 83772 83721 0 0
T165 65848 65797 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 3191 0 0
T6 82209 1064 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1063 0 0
T217 0 1064 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 0 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 3191 0 0
T6 82209 1064 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1063 0 0
T217 0 1064 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 3191 0 0
T6 82209 1064 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1063 0 0
T217 0 1064 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 3191 0 0
T6 82209 1064 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1063 0 0
T217 0 1064 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 3191 0 0
T6 82209 1064 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1063 0 0
T217 0 1064 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 499487731 0 0
T4 93806 93755 0 0
T5 115592 115533 0 0
T6 82209 82158 0 0
T17 282697 282595 0 0
T18 389620 389558 0 0
T19 322594 322362 0 0
T31 296751 296745 0 0
T114 293032 292923 0 0
T142 83772 83721 0 0
T165 65848 65797 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508532396 3191 0 0
T6 82209 1064 0 0
T17 282697 0 0 0
T18 389620 0 0 0
T19 322594 0 0 0
T31 296751 0 0 0
T57 150680 0 0 0
T114 293032 0 0 0
T136 462483 0 0 0
T142 83772 0 0 0
T165 65848 0 0 0
T179 0 1063 0 0
T217 0 1064 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%